Reversible Combinational Circuits Research Articles

Novel design of reversible latches using feynman gate and implementation of reversible combinational circuits

Novel design of reversible latches using feynman gate and implementation of reversible combinational circuits

DESIGN OF ADDER AND SUBTRACTOR HAVING LESS POWER DISSIPATION

With the advancement in technology in the field of digital electronics, reversible logical has become a powerful tool in wide variety of areas like in designing of low power VLSI circuits, DNA computing, quantum computing and optical computing. Circuits made using reversible logic are more energy efficient and consumes less power. In these modern times we need designs of circuits that are speed efficient and should also consume less power. This paper emphasizes on presenting the improved reversible combinational circuit of eight – bit parallel adder and subtractor. These circuits are designed and implemented using Feynman, Double Feynman and MUX gates. Three designs of reversible eight – bit parallel adder and subtractor is proposed. Performance of all three designs is analyzed based number of reversible gates required, garbage input and output, quantum cost.

Design and Implementation of CNTFET-Based Reversible Combinational Digital Circuits Using the GDI Technique for Ultra-low Power Applications

It is obvious that the design of low power digital circuits is very important. Hence, reversible logic can be used as the great method for reducing power consumption. In this paper, we attempt to present various CNTFET-based reversible combinational circuits such as multiplexers and decoders by simultaneous use of the reversible Fredkin gate and Gate Diffusion Input (GDI) technique. At first, we illustrate the block diagram of multiplexers and decoders according to the definition of reversible gates. Then, we introduce the design approach of CNTFET-based circuits by using the GDI technique. All structures are simulated using Synopsys HSPICE with standard 32 nm CNTFET technology in various conditions including temperature 27 °C, simulation time from zero to 100 ns, and other parameters are the variable. In this work, we investigate the variation effect of supply voltage, temperature, number of nanotubes, and chiral vector in performance evaluation of the mentioned circuits. In addition, the ECPOT analysis is reported. According to the results, the proposed CNTFET-based reversible multiplexers achieve a significant saving in average power consumption (approximately 99.99% for 2:1 multiplexer, 99.95% for 4:1 multiplexer, 99.96% for 8:1 multiplexer compared with the best previous work) and the average power consumption for 16:1 multiplexer is 25.47 nw. The proposed CNTFET-based reversible decoders have high performance in the average power consumption (approximately 99.99% for 2:4 decoder, 99.99% for 3:8 decoder, and 99.22% for 4:16 decoder compared with the best previous work). Moreover, applying these suggested circuits significantly improves the speed, PDP, and EDP of complex arithmetic structures.

Design of Reversible Synchronous Sequential Circuits Using Pseudo Reed-Muller Expressions

Reversible logic has become very promising for low-power design using emerging computing technologies. A number of good works have been reported on reversible combinational circuit design. However, only a few works reported on the design of reversible latches and flip-flops on the top of reversible combinational gates and suggested that sequential circuits be built by replacing the latches and flip-flops and associated combinational gates of the traditional irreversible designs by their reversible counter parts. This replacement technique is not very promising, because it leads to high quantum cost and garbage outputs. In this paper, we propose a novel approach of designing synchronous sequential circuits directly from reversible gates using pseudo Reed-Muller expressions representing the state transition and the output functions of the circuit. We present designs of arbitrary synchronous sequential circuit as well as practically important sequential circuits such as counters and registers. It is found that our direct designs save 1.54%-49.09% quantum cost and 51.43%-81.82% garbage outputs than the replacement design approach suggested earlier.

Fault diagnosis in reversible circuits under missing-gate fault model

This article presents a novel technique for fault detection as well as fault location in a reversible combinational circuit under the missing gate fault model. It is shown that in an (nxn) reversib...

Fault diagnosis in reversible circuits under missing-gate fault model

This article presents a novel technique for fault detection as well as fault location in a reversible combinational circuit under the missing gate fault model. It is shown that in an ( n × n) reversible circuit implemented with k-CNOT gates, addition of only one extra control line along with duplication each k-CNOT gate, yields an easily testable design, which admits a universal test set (UTS) of size ( n + 1) that detects all single missing-gate faults (SMGFs), repeated-gate faults (RGFs), and partial missing-gate faults (PMGFs) in the circuit. Furthermore, storage of only one vector (seed) of the UTS is required; the rest can be generated by n successive cyclic bit-shifts from the seed. For fault location under the SMGF model, a technique for identifying the faulty gate is also presented that needs application of a single test vector, provided the circuit is augmented with some additional observable outputs.