Reverse Back Bias Research Articles

Ultra-low voltage and energy efficient adders in 28 nm FDSOI exploring poly-biasing for device sizing

Balancing the PMOS/NMOS strength ratio is a key issue to maximize the noise margin, and hence, the functional yield of CMOS logic gates and minimize the leakage energy per cycle in the subthreshold region. In this work, the PMOS/NMOS strength ratio was balanced using a poly-biasing technique in conjunction with back-gate biasing provided in a 28 nm fully depleted silicon on insulator (FDSOI) CMOS technology. A 32-bit adder based on minority-3 (min-3) gates and a 16-bit adder based on Boolean gates have been implemented. Chip measurement results of nine samples show highly energy efficient adders. The 32-bit and 16-bit adders achieved mean minimum energy points (MEP) of 20.8 fJ at 300 mV and 12.34 fJ at 250 mV, respectively. In comparison to adders reported in other works in the same technology, the energy per 1-bit addition of the 32-bit adder is improved by 37%. This improvement in energy consumption is 25% for the 16-bit adder. According to the measurement results of ten chips, the designed adders exhibited functionality down to supply voltages of 110 mV-125 mV, without body biasing. Additionally, the minimum Vdd of all the 32-bit adders based on minority-3 gates decreased to 80 mV by applying a reverse back bias voltage to the PMOS devices. One sample was functional at 79 mV with a 430 mV reverse back bias voltage applied to its PMOS devices.

(Keynote) FDSOI Past, Present and Future

FDSOI is quickly becoming a technology offering that can deliver next generation performance with superior low power operation at a significant cost advantage. Researchers have actively pursued alternatives to conventional bulk and PDSOI transistors for well over 10 years. However, there was not enough compelling need to change until conventional CMOS scaling dramatically slowed. Beyond the 28nm node new device architectures were needed to continue the scaling trend. FDSOI was always thought to be an attractive option since of all the alternative approaches it is the most similar to conventional bulk or PDSOI. This is mainly due to the fact that it is planar and thus much of the process and design methodology can be re used from previous nodes. On the other hand several key issues for FDSOI were known and thought to be fundamental challenges. Specifically silicon consumption, high external resistance and parasitic capacitance were identified as major hurdles. FDSOI relies upon the thin channel to control short channel effects. For example a channel thickness of approximately 6nm is required to maintain good electrostatics for a transistor with Lg=20nm. Maintaining thin silicon in the channel while still preserving silicon in the source-drain regions is a big process challenge. We have carefully optimized several key process steps including the spacer etch process to eliminate excessive silicon consumption. As shown in Fig. 1 the zero loss spacer process features a partial etch using reactive ion etching. In order to minimize silicon consumption, the spacer etch is terminated before the spacer material is completely removed from the horizontal surfaces and the dry etch cannot consume silicon. The residual spacer material is removed as part of the pre epi clean for raised source-drain. Since the wet etch for the pre-clean is highly selective to the silicon, there is no silicon consumption. High external resistance was thought to be a significant challenge for FDSOI mainly in part due to the silicon consumption from the spacer process but also from the junction formation process. Ion implantation is well known to cause damage in thin silicon even with high temperature activation anneal. The silicon damage caused by the ion implantation can also cause defective epitaxial growth during the raised source drain process. We have solved the challenge of junction formation for FDSOI by developing an implant last scheme. After the spacer module is completed the raised-source and drain is formed. Since the ion implant is done into the thick raised-source drain, the damage created is healed during the activation anneal. Parasitic capacitance is another known issue for devices with raised-source drain. We have developed a facetted epi process which eliminates a significant component of the additional parasitic capacitance caused by the raised-source drain (Fig. 2). 1 We have also developed several key elements that enable high performance FDSOI circuits. In-situ doped SiGeB for raised source-drain has been developed to reduce contact resistance and form abrupt junctions for pFETs. SiGe channel is another innovation we have developed to enable high performance by increasing hole mobility. Fig. 3 shows the benefit of the strained SiGe raised source-drain and the SiGe channel.2 FDSOI is scalable and can be used for several technology nodes. Gate length scaling for FDSOI can be accomplished by thinning the silicon. Reverse back bias can also be used to improve short channel effects and enable scaling. Figure 4 shows the improvement in short channel control as the silicon is thinned down to 3.5nm Remarkably the external resistance of the devices is not compromised as evidenced by the Ion vs Ioff comparison to devices with 6nm channel thickness. The same figure also shows the improvement in electrostatic behavior with reverse back bias.3 Additional improvements in FDSOI performance can be achieved by strained silicon on insulator technology. Figure 5 shows the benefit of the strained silicon channel for nFETs.4 Table 1 shows a comparison of state of the art FDSOI research transistors to FinFETs.5It is interesting to note that the FDSOI devices can achieve competitive drive currents at dramatically shorter gate-lengths thereby improving circuit performance. It is also interesting to note the FinFETs are normalized to the footprint which is 30% greater than the effective channel width. References K. Cheng et. al. IEDM 2010.K. Cheng et. al. IEDM 2013.A. Khakifirooz et. al. EDL 2012.A. Khakifirooz et. al. VLSI 2012.Q. Liu et. al. IEDM 2014. Figure 1

First Demonstration of Junctionless Accumulation-Mode Bulk FinFETs With Robust Junction Isolation

A junctionless-accumulation-mode (JAM) p-channel MOSFET is successfully implemented based on a junction-isolated bulk FinFET for the first time. The JAM devices with a fin width of 16 nm show outstanding transfer characteristics: 1) subthreshold swing (SSmin) = 68 mV/dec; 2) drain-induced-barrier-lowering is 9 mV/V; and 3) ION/IOFF ratio >1 × 106. The JAM devices with smaller fin widths or longer gate lengths give superior short-channel characteristics and higher threshold voltages (Vth) due to their enhanced gate electrostatic controllability. The reverse back bias modulates Vth and SS favorably by virtue of a body-tied device, maintaining the substrate current due to junction leakage of <;1 × 10-11 A.

Back-Gate Bias Dependence of the Statistical Variability of FDSOI MOSFETs With Thin BOX

The impact of back-gate bias on the statistical variability (SV) of FDSOI MOSFETs with thin buried oxide (BOX) is studied via 3-D “atomistic” drift-diffusion simulation. The impact of the principal sources of SV, i.e., random dopant fluctuations, line edge roughness, and metal gate granularity, on threshold voltage, drain-induced barrier lowering, and drive current is studied in detail. It is shown that reverse back-bias is beneficial in terms of reducing the dispersion of the off-current and the corresponding standby leakage power, whereas forward back-bias reduces the on -current variability. The correlation coefficients between relevant figures of merit and their trends against back-bias are also studied in detail, providing guidelines for the development of statistical compact models of thin-BOX FDSOI MOSFETs for low-standby-power circuit applications.

Mixed FBB/RBB: A Novel Low-Leakage Technique for FinFET Forced Stacks

In this paper, a novel technique to reduce the leakage current of FinFET forced stacks under a given delay constraint is presented. This technique takes advantage of the unique feature of four-terminal FinFETs allowing different transistors to have separately tunable back bias voltages. In this work, a reverse back bias voltage is applied to one of the two stacked transistors to reduce its leakage at the cost of a delay penalty, whereas a forward back bias voltage is applied to the other one to compensate this delay degradation. The technique is assessed by means of mixed device-circuit simulations for FinFETs that are representative of 40- and 27-nm technology generations. Results show that a leakage reduction by up to 50× can be achieved as compared with traditional transistor stacks, while keeping same speed, dynamic energy, and sensitivity to process/voltage/temperature variations.

Planar GeOI TFET Performance Improvement With Back Biasing

Reverse back biasing of a planar germanium-on-insulator tunneling field-effect transistor provides for significant improvement in ION/IOFF, by over an order of magnitude for 0.25 V operating voltage. Optimization of the gate-to-source overlap and source doping gradient is key to maximizing the benefit of back biasing.

SOI TFET $I_{\rm ON}/I_{\rm OFF}$ Enhancement via Back Biasing

The effect of back biasing on the performance of a planar tunnel field-effect transistor (TFET) implemented on a silicon-on-insulator substrate is investigated. It is found that reverse back biasing reduces the subthreshold swing SS and increases the range of drain current over which SS is less than ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">q</i> ) <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ln</i> (10); hence, it is effective for improving the TFET on/off current ratio for low operating voltages (≤ 0.5 V).