Crossbar Resistive Random Access Memory Research Articles

Modeling of Self-Aligned Selector Based on Ultra-Thin Metal Oxide for Resistive Random-Access Memory (RRAM) Crossbar Arrays.

Resistive random-access memory (RRAM) is a crucial element for next-generation large-scale memory arrays, analogue neuromorphic computing and energy-efficient System-on-Chip applications. For these applications, RRAM elements are arranged into Crossbar arrays, where rectifying selector devices are required for correct read operation of the memory cells. One of the key advantages of RRAM is its high scalability due to the filamentary mechanism of resistive switching, as the cell conductivity is not dependent on the cell area. Thus, a selector device becomes a limiting factor in Crossbar arrays in terms of scalability, as its area exceeds the minimal possible area of an RRAM cell. We propose a tunnel diode selector, which is self-aligned with an RRAM cell and, thus, occupies the same area. In this study, we address the theoretical and modeling aspects of creating a self-aligned selector with optimal parameters to avoid any deterioration of RRAM cell performance. We investigate the possibilities of using a tunnel diode based on single- and double-layer dielectrics and determine their optimal physical properties to be used in an HfOx-based RRAM Crossbar array.

Improved Arithmetic Performance by Combining Stateful and Non‐Stateful Logic in Resistive Random Access Memory 1T–1R Crossbars

Computing‐in‐memory (CIM) is a promising approach for overcoming the memory‐wall problem in conventional von‐Neumann architectures. This is done by performing certain computation tasks directly in the storage subsystem without transferring data between storage and processing units. Stateful and non‐stateful CIM concepts are recently attracting lots of interest, which are demonstrated as logical complete, energy efficient, and compatible with dense crossbar structures. However, sneak‐path currents in passive resistive random access memory (RRAM) crossbars degrade the operation reliability and require the usage of active 1 Transistor–1 Resistance (1T‐1R) bitcell designs. In this article, the arithmetic performance and reliability are investigated based on experimental measurements and variability‐aware circuit simulations. Herein, it is aimed for the evaluation of logic operations specifically with fully integrated 1T–1R crossbar devices. Based on these operations, an N‐bit full adder with optimized energy consumption and latency is demonstrated by combining stateful and non‐stateful CIM logic styles with regard to the specific conditions in active 1T–1R RRAM crossbars.

Mathematical Framework for Optimizing Crossbar Allocation for ReRAM-based CNN Accelerators

The resistive random-access memory (ReRAM) has widely been used to accelerate convolutional neural networks (CNNs) thanks to its analog in-memory computing capability. ReRAM crossbars not only store layers’ weights, but also perform in-situ matrix-vector multiplications which are core operations of CNNs. To boost the performance of ReRAM-based CNN accelerators, crossbars can be duplicated to explore more intra-layer parallelism. The crossbar allocation scheme can significantly influence both the computing throughput and bandwidth requirements of ReRAM-based CNN accelerators. Under the resource constraints (i.e., crossbars and memory bandwidths), how to find the optimal number of crossbars for each layer to maximize the inference performance for an entire CNN is an unsolved problem. In this work, we find the optimal crossbar allocation scheme by mathematically modeling the problem as a constrained optimization problem and solving it with a dynamic programming based solver. Experiments demonstrate that our model for CNN inference time is almost precise, and the proposed framework can obtain solutions with near-optimal inference time. We also emphasize that communication (i.e., data access) is an important factor and must also be considered when determining the optimal crossbar allocation scheme.

An Energy-Efficient Inference Engine for a Configurable ReRAM-Based Neural Network Accelerator

Resistive random-access memory (ReRAM) offers a potential solution to accelerate the inference of deep neural networks by performing processing-in-memory. However, the peripheral circuits of ReRAM crossbars used to perform arithmetic operations consume significant amounts of power. Based on a power consumption analysis of the ReRAM crossbar circuits, we propose using the dynamic reference voltage scalable analog-to-digital circuits (ADCs) to conduct the dot product operation to enable the reconfigurability of the ReRAM-based neural network (NN) accelerator while maintaining accuracy. We propose a configurable ReRAM-based NN accelerator to provide various degrees of computing granularity with different levels of power consumption, creating a tradeoff between performance and power consumption in the given NN. Next, we develop an energy-efficient inference engine for the configurable ReRAM-based NN accelerator, EIF, to assign the operation unit (OU) size to perform vector-matrix multiplication (VMM) based on the data dependence of the NN. Our evaluation shows that the proposed EIF provided an energy savings of up to 36% over the state-of-the-art ReRAM-based accelerator while maintaining performance without resource duplication.

A Practical Highly Paralleled ReRAM-Based DNN Accelerator by Reusing Weight Pattern Repetitions

Resistive random access memory (ReRAM)-based processing-in-memory (PIM) architecture has been designed to accelerate deep neural networks (DNNs) by concurring computation and memory barriers. To further improve memory and computation efficiency, the weight sparsity characteristic has been explored to optimize the ReRAM-based DNN accelerators. However, these designs only focus on compressing zero weights to eliminate ineffectual computation. In this article, we thoroughly analyze the weight distribution characteristics of several typical DNN models and observe many nonzero weight pattern repetitions (WPRs). Therefore, there is an opportunity to further improve the performance and energy efficiency by reusing these WPR. We propose a novel ReRAM-based accelerator—PattPIM, to achieve space compression and computation reuse by exploring DNN WPR based on practical ReRAM crossbars. In PattPIM, we propose a configurable WPR-aware DNN engine and a WPR-to-OU mapping scheme to save both space and computation resources. An intraprocessing engine (PE) pipeline is designed to improve the parallelism of the computation process. Furthermore, we adopt an approximate weight pattern transform algorithm to improve the DNN WPR ratio to enhance the reuse efficiency with negligible accuracy loss. Our evaluation with 6 DNN models shows that the proposed PattPIM delivers significant performance improvement, ReRAM resource efficiency and energy saving.

EnTiered-ReRAM: An Enhanced Low Latency and Energy Efficient TLC Crossbar ReRAM Architecture

Resistive Random Access Memory (ReRAM) is promising to be employed as high density storage-class memory due to its crossbar array and Triple-Level Cell (TLC) structures. However, TLC crossbar ReRAM suffers from high write latency and energy due to three unique challenges: (1) The crossbar array structure incurs IR drop issues. (2) The TLC structure requires iterative program-and-verify (P&V) procedure. (3) The resistance drift problem needs short interval scrub to avoid uncorrectable soft errors. In this article, to overcome the challenges of TLC crossbar ReRAM, we propose an enhanced low latency and energy efficient TLC crossbar ReRAM architecture, called EnTiered-ReRAM. The proposed EnTiered-ReRAM is composed of four components, including EnTiered-crossbar design, Compression-based Incomplete Data Mapping (CIDM), Compression-based Flip Scheme (CFS), and Compression-based Error Correction Code (CECC). Specifically, based on the observation that our previously proposed Tiered-crossbar design still suffers from large IR drops along bitlines in the far segments due to the long length of bitlines, EnTiered-crossbar partitions each crossbar array into two halves along bitlines, and then splits each bitline of the half crossbar array into the near and far segments by an isolation transistor, which thoroughly mitigates the IR drop issues. Then we use our previously proposed CIDM and CFS in the near and far segments of EnTiered-crossbar arrays to further decreases the write latency and energy. In addition, CECC is deeply coupled with CIDM and CFS. CECC dynamically employs the most appropriate ECC capability according to the remaining space of each cache line after CIDM or CFS encoding, which effectively improves the scrub interval and performance/energy with insignificant space overhead. The evaluation results show that, compared with an aggressive baseline, EnTiered-ReRAM can improve the system performance by 56.3% and reduce the energy consumption by 60.6% on average.

STAR: Synthesis of Stateful Logic in RRAM Targeting High Area Utilization

Processing-in-memory (PIM) exploits massive parallelism with high energy efficiency and becomes a promising solution to the von Neumann bottleneck. Recently, the emerging metal-oxide resistive random access memory (RRAM) shows its potential to construct a PIM architecture, because several stateful logic operations, e.g., IMP and NOR, can be executed in an RRAM crossbar in parallel. Previous synthesis flows focus on improving latency with stateful logic operations, but they ignore that the memory should be used primarily for storage. i.e., most of the area in the crossbar is used for computation but not storage. In this situation, storage and computation still have to be separated into different crossbars, which leads to considerable data transfer overhead and limited parallelism. In this work, we define the ratio of storage in a crossbar as area utilization. We aim to improve the area utilization without throughput loss by proposing STAR, a novel synthesis flow for the stateful logic. We present two optimization strategies to reduce the computation area in STAR. First, we reduce the area for redundant inputs. For the shared constants among different rows (or columns), we encode them as immediate values into the control signals without writing them into the crossbar at runtime. For the other inputs, we only store one copy of them in the crossbar. Second, we reduce the area for intermediate variables by reusing invalid cells. And we design a scheduling algorithm to find a computation sequence with the minimal variable erasing cycles. Invalid primary inputs can also be erased in this algorithm. Furthermore, we present a case study of the image convolution to demonstrate the effectiveness of STAR. Experimental evaluation shows that STAR achieves 33.03% more area utilization and a 1.43x throughput compared to SIMPLER, the state-of-the-art stateful logic synthesis flow. Our image convolution implementation also provides 78.36% more area utilization and a 1.48x throughput compared with IMAGING, the state-of-the-art stateful logic-based image processing accelerator.

ERA-LSTM: An Efficient ReRAM-Based Architecture for Long Short-Term Memory

Processing-in-memory (PIM) architecture based on resistive random access memory (ReRAM) crossbars is a promising solution to the memory bottleneck that long short-term memory (LSTM) faces. Based on the dataflow analysis of the LSTM computing paradigm, this article proposes to adopt the ReRAM-based analog approximate computing to conduct the LSTM-specific element-wise computation. Combined with the dot-product computation implemented with ReRAM crossbars, a new LSTM processing tile is designed to significantly reduce the demand for analog-to-digital converters (ADCs), which is the major part of power consumption of existing designs. Next, we elaborate on a mapping scheme to efficiently deploy large-scale LSTM onto multiple processing tiles. Finally, an architecture enhancement is proposed to support crossbar-friendly LSTM pruning to further improve efficiency. This overall design, named ERA-LSTM, is presented. Our evaluation shows that it can outperform two state-of-the-art FPGA-based LSTM accelerators by 103.6 and 35.9 times, respectively; compared with a state-of-the-art ReRAM-based LSTM accelerator with digital element-wise computation, it is 6.1 times more efficient. Moreover, our experiments demonstrate that the impact of hardware constraints and approximation errors on the inference accuracy can be effectively reduced by the proposed fine-tuning scheme and by optimizing the design of the approximator.

A Fully Integrated Reprogrammable CMOS-RRAM Compute-in-Memory Coprocessor for Neuromorphic Applications

Analog compute-in-memory with resistive random access memory (RRAM) devices promises to overcome the data movement bottleneck in data-intensive artificial intelligence (AI) and machine learning. RRAM crossbar arrays improve the efficiency of vector-matrix multiplications (VMMs), which is a vital operation in these applications. The prototype IC is the first complete, fully integrated analog-RRAM CMOS coprocessor. This article focuses on the digital and analog circuitry that supports efficient and flexible RRAM-based computation. A passive $54\times108$ RRAM crossbar array performs VMM in the analog domain. Specialized mixed-signal circuits stimulate and read the outputs of the RRAM crossbar. The single-chip CMOS prototype includes a reduced instruction set computer (RISC) processor interfaced to a memory-mapped mixed-signal core. In the mixed-signal core, ADCs and DACs interface with the passive RRAM crossbar. The RISC processor controls the mixed-signal circuits and the algorithm data path. The system is fully programmable and supports forward and backward propagation. As proof of concept, a fully integrated 0.18- $\mu \text{m}$ CMOS prototype with a postprocessed RRAM array demonstrates several key functions of machine learning, including online learning. The mixed-signal core consumes 64 mW at an operating frequency of 148 MHz. The total system power consumption considering the mixed-signal circuitry, the digital processor, and the passive RRAM array is 307 mW. The maximum theoretical throughput is 2.6 GOPS at an efficiency of 8.5 GOPS/W.

ITT-RNA: Imperfection Tolerable Training for RRAM-Crossbar-Based Deep Neural-Network Accelerator

Deep neural networks (DNNs) have gained a strong momentum among various applications. The enormous matrix-multiplication exhibited in the above DNNs is computation and memory intensive. Resistive random-access memory crossbar (RRAM-crossbar) consisting of memristor cells can naturally carry out the matrix-vector multiplication. RRAM-crossbar-based accelerator, therefore, has two orders of magnitude of higher energy-efficiency than conventional accelerators. The imperfect fabrication process of RRAM-crossbars, however, causes various defects and process variations. These fabrication imperfections not only result in significant yield loss but also degrade the accuracy of DNNs executed on the RRAM-crossbars. In this article, we first propose an accelerator-friendly neural-network training method, by leveraging the inherent self-healing capability of the neural network, to prevent the large-weight synapses from being mapped to the imperfect memristors. Next, we propose a dynamic adjustment mechanism to extend the above method for DNNs, such as multilayer perceptrons (MLPs), wherein the imperfect-memristor induced errors can accumulate and magnify through multiple layers. Such off-device training method is a pure software solution, and it is unable to provide enough accuracy for convolutional neural networks (CNNs). Several works propose error-tolerable hardware design by allowing the retraining of CNNs on the RRAM-crossbar. Although this hardware-based on-device training method is effective, the frequent write operation on RRAM-crossbar hurt the endurance of RRAM-crossbars. Consequently, we propose a software and hardware co-design methodology to effectively preserve the classification accuracy of CNN with few on-device training iterations. The experimental results show that the proposed method can guarantee ≤1.1% loss of accuracy for resistance variations in MLP and CNN. Moreover, the proposed method can guarantee ≤1% loss of accuracy even when stuck-at-faults (SAFs) rate = 20%.

A Compact Model of Analog RRAM With Device and Array Nonideal Effects for Neuromorphic Systems

The parallelism and analog computing features of neuromorphic systems bring great challenges in developing a compact model of analog resistive random access memory (RRAM). In this article, we develop a physics-based compact model for analog RRAM devices and crossbar array. Nonideal effects of analog RRAM device, such as variability, ${I}$ – ${V}$ nonlinearity, programming nonlinearity and asymmetry, and tuning voltage sensitivity, are modeled and verified with the statistical data measured from RRAM array. Modeling of parallel-vector-matrix-multiplication and weight update process on RRAM crossbars with interconnect resistance enables fast and accurate estimation of the training accuracy. Benchmarks of neural networks under different hardware conditions validate the functionality of the proposed model. This model can provide valuable design guidelines for a practical neuromorphic system with high performance and computing accuracy.

Pilot Assisted Adaptive Thresholding for Sneak-Path Mitigation in Resistive Memories With Failed Selection Devices

Resistive random-access memory (ReRAM) with the crossbar structure is one promising candidate to be used as a next generation non-volatile memory device. In a crossbar ReRAM, in which a memristor is positioned on each row-column intersection, the sneak-path problem is one of the main challenges for a reliable readout. The sneak-path problem can be solved with additional selection devices. When some selection devices fail short, the sneak-path problem re-occurs. The re-occurred sneak-path problem is addressed in this paper. The re-occurred sneak-path event can be described combinatorially and its adverse effect can be modeled as a parallel interference. Based on a simple pilot construction, we probabilistically characterize the inter-cell dependency of the re-occurred sneak-path events. Utilizing this dependency, we propose adaptive thresholding schemes for resistive memory readout using side information provided by pilot cells. This estimation theoretic approach effectively reduces the bit-error rate while maintaining low redundancy overhead and low complexity.

HyVE: Hybrid Vertex-Edge Memory Hierarchy for Energy-Efficient Graph Processing

High energy consumption of conventional memory modules (e.g., DRAMs) hinders the further improvement of large-scale graph processing’s energy efficiency. The emerging resistive random-access memory (ReRAM) has shown great potential in providing an energy-efficient memory module. However, the performance of ReRAMs suffers from data access patterns with poor locality and large amounts of written data, which are common in graph processing. In this paper, we propose HyVE, a Hybrid Vertex-Edge memory hierarchy for energy-efficient graph processing. In HyVE, we avoid random access and data written to ReRAM modules. HyVE can reduce memory energy consumption by 86.17 percent compared with conventional memory systems. We have also proposed data sharing and bank-level power-gating schemes, which improve the energy efficiency by 1.60x and 1.53x. By analyzing the graph processing model on ReRAMs, we show that ReRAMs are good for read-intensive operations in graph processing (e.g., reading edges), while ReRAM crossbars are not suitable for processing edges because of heavy writing overheads. Our evaluations show that the optimized design achieves two orders of magnitude and 5.90x energy efficiency improvement compared with the CPU-based and conventional memory hierarchy based designs, respectively. Moreover, HyVE achieves 2.83x energy reduction compared with the previous ReRAM-based graph processing architecture.

Nanoscale 3D Stackable Ag-Doped HfOx-Based Selector Devices Fabricated through Low-Temperature Hydrogen Annealing.

Electrochemical metallization-based threshold switching devices with active metal electrodes have been studied as a selector for high-density resistive random access memory (RRAM) technology in crossbar array architectures. However, these devices are not suitable for integration with three-dimensional (3D) crossbar RRAM arrays due to the difficulty in vertical stacking and/or scaling into the nanometer regime as well as the asymmetric threshold switching behavior and large variation in the operating voltage. Here, we demonstrate bidirectional symmetric threshold switching behaviors from a simple Pt/Ag-doped HfOx/Pt structure. While fabricating the Pt/Ag-doped HfOx/Pt film using a 250 nm hole structure, filaments composed of Ag nanoclusters were constructed through a low-temperature (∼200 °C) hydrogen annealing process where the shape of the film in a nanoscale via a hole structure was maintained for integration with 3D stackable crossbar RRAM arrays. Finite Ag filament paths in the HfOx layer led to uniform device-to-device performances. Moreover, we observed that the hydrogen annealing process reduced the delay time through the reduction of the oxygen vacancies in the HfOx layer. Consequently, the proposed Pt/Ag-doped HfOx/Pt-based nanoscale selector devices exhibited excellent performance of high selectivity (∼105), ultralow OFF current (∼10 pA), steep turn-on slope (∼2 mV/decade), and short delay time (3 μs).

Memory state protected from leakage current in Ti/SiN/NiN/Pt bilayer resistive random-access memory devices for array applications

In this work, we present a method to protect the memory state of Pt/NiN/SiN/Ti bilayer memory structures, to integrate resistive switching memory with bipolar resistive switching (BRS) elements into a cross bar array (CBA) structure. In the device, a silicon nitride (SiN) layer acts as area creating BRS, while a nickel nitride (NiN) layer can be used as a selector (S), which results in the selector free resistive random-access memory (RRAM) devices possible to directly integrate into a CBA structure, without the need of additional elements. In addition, the proposed RRAM device shows a stable current ratio of >101 in the repetitive direct current cycling test of 200 times, a long retention time of >105, and a wide read-out margin of 130, which indicates the sneak current path in the crossbar structures was significantly suppressed. We believe that the proposed architecture is a strong candidate for future cross-bar type RRAM applications.

3D characterization of hard breakdown in RRAM device

Resistive Random Access Memory (RRAM) device is considered as a promising NVM device to replace flash memory device due to its simple design, small size and low operating conditions. The reliability of RRAM devices has been studied with respect to endurance, retention and variability for many years. However, the increasing demand of high performance and drastic down scaling trend make the reliability issues more challenging than before. In this work, a comprehensive study of hard breakdown (HBD) process in crossbar RRAM device was carried out via electrical, compositional and structural characterization methods. The results confirm that the HBD process was caused by Ta2O5 dielectric breakdown with intensive joule heating and melting process. The 3D structures of defects are well reconstructed. The percolation path was confirmed to be located at the edges of crossbar structure due to the low quality of peripheral materials and process variation. The presented work can offer a critical insight on preventing the HBD process in crossbar RRAM structure.

TIME: A Training-in-Memory Architecture for RRAM-Based Deep Neural Networks

The training of neural networks (NN) is usually time-consuming and resource intensive. The emerging metal-oxide resistive random-access memory (RRAM) device has shown potential for the computation of NN. RRAM crossbar structure and multibit characteristics can perform the matrix-vector product in high energy efficiency, which is the most common operation of NN. Two challenges exist for realizing training NN based on RRAM. First, the current architectures based on RRAM only support the inference in training NN and cannot perform the backpropagation (BP) and the weight update of training NN. Second, training NN requires enormous iterations to constantly update the weights for reaching the convergence. However, this weight update leads to large energy consumption because of the nonideal factors of RRAM. In this paper, we propose a training-in-memory based on RRAM (TIME) architecture and the peripheral circuit design to enable training NN on RRAM. TIME supports the BP and the weight update while maximizing the re-usage of peripheral circuits of the inference operation on RRAM. Meanwhile, a set of optimization strategies focusing on the nonideal factors are designed to reduce the cost of tuning RRAM. We explore the performance of both supervised learning (SL) and deep reinforcement learning (DRL) on TIME. A specific mapping method of DRL is also introduced to further improve energy efficiency. Simulation results show that in SL, TIME can achieve $5.3{\times }$ higher energy efficiency on average compared with DaDianNao, an application-specific integrated circuits (ASIC) in CMOS technology. In DRL, TIME can perform an average $126{\times }$ higher than GPU in energy efficiency. If the cost of tuning RRAM can be further reduced, TIME has the potential to boost the energy efficiency by two orders of magnitudes compared with ASIC.

A Secure Integrity Checking System for Nanoelectronic Resistive RAM

Recent advances in resistive random access memory (RRAM) as high density, low power, and faster memory systems drive the need for devising a more lightweight integrity checking system for RRAM. In this paper, we design a new tag generation system for integrity checking of RRAM. A single read operation to a crossbar RRAM in the presence of sneak path currents can output a tag for the memory data that can be used for integrity checking. An analytical approach to model such a tag generation process is described in this paper. Security results predicted by the analytical model provide various design options leading to an optimal system from the perspective of considered security properties. The proposed design is simulated to investigate and verify the security properties of the system for a number of optimal design options predicted by the analytical model. Reliability of the proposed system is also measured for varying conditions of device parameters, operating temperatures, load resistances, and read voltage. Finally, the performance of the proposed system is compared against another existing lightweight tag generation method from the perspective of energy consumption, transistor count, and delay.

Sign backpropagation: An on-chip learning algorithm for analog RRAM neuromorphic computing systems

Currently, powerful deep learning models usually require significant resources in the form of processors and memory, which leads to very high energy consumption. The emerging resistive random access memory (RRAM) has shown great potential for constructing a scalable and energy-efficient neural network. However, it is hard to port a high-precision neural network from conventional digital CMOS hardware systems to analog RRAM systems owing to the variability of RRAM devices. A suitable on-chip learning algorithm should be developed to retrain or improve the performance of the neural network. In addition, determining how to integrate the periphery digital computations and analog RRAM crossbar is still a challenge. Here, we propose an on-chip learning algorithm, named sign backpropagation (SBP), for RRAM-based multilayer perceptron (MLP) with binary interfaces (0, 1) in forward process and 2-bit (±1, 0) in backward process. The simulation results show that the proposed method and architecture can achieve a comparable classification accuracy with MLP on MNIST dataset, meanwhile it can save area and energy cost by the calculation and storing of the intermediate results and take advantages of the RRAM crossbar potential in neuromorphic computing.

CACF

Emerging Resistive Random Access Memory (ReRAM) is a promising candidate as the replacement for DRAM due to its low standby power, high density, high scalability, and nonvolatility. By employing the unique crossbar structure, ReRAM can be constructed with extremely high density. However, the crossbar ReRAM faces some serious challenges in terms of performance, reliability, and energy consumption. First, ReRAM’s crossbar structure causes an IR drop problem due to wire resistance and sneak currents, which results in nonuniform access latency in ReRAM banks and reduces its reliability. Second, without access transistors in the crossbar structure, write disturbance results in serious data reliability problem. Third, the access latency, reliability, and energy use of ReRAM arrays are significantly influenced by the data patterns involved in a write operation. To overcome the challenges of the crossbar ReRAM, we propose a novel circuit architecture co-optimization framework for improving the performance, reliability, and energy use of ReRAM-based main memory system, called CACF. The proposed CACF consists of three levels, including the circuit level, circuit architecture level, and architecture level. At the circuit level, to reduce the IR drops along bitlines, we propose a double-sided write driver design by applying write drivers along both sides of bitlines and selectively activating the write drivers. At the circuit architecture level, to address the write disturbance with low overheads, we propose a RESET disturbance detection scheme by adding disturbance reference cells and conditionally performing refresh operations. At the architecture level, a region partition with address remapping method is proposed to leverage the nonuniform access latency in ReRAM banks, and two flip schemes are proposed in different regions to optimize the data patterns involved in a write operation. The experimental results show that CACF improves system performance by 26.1%, decreases memory access latency by 22.4%, shortens running time by 20.1%, and reduces energy consumption by 21.6% on average over an aggressive baseline. Meanwhile, CACF significantly improves the reliability of ReRAM-based memory systems.