Residue Number System Architecture Research Articles

A Novel RNS Hardware Architecture of FRM Filter Banks for Digital Hearing Aids

This paper presents a novel hardware architecture for Frequency Response Masking (FRM) Filter Bank based on Residue Number System (RNS) arithmetic for Digital Hearing Aids (DHA). FRM is a computationally efficient approach for filter bank design that separates different frequencies based on the Audiograms of a patient. However, filter banks are critical power-hungry elements that require high computational resources. Therefore, the proposed architecture aims to provide an efficient implementation of FRM filter banks, which can improve the value and affordability of DHAs. The proposed architecture employs FIR filters in direct form, linear phase, and poly phase using RNS arithmetic. This approach enables the performance of arithmetic operations in parallel and independently. The concepts are further extended for the efficient implementation of FRM filter bank. The results of the proposed architecture show that direct implementation reduces the delay when the number of taps increases in the FIR filter. However, to reduce computational resources and optimize the area requirement, a Folded RNS architecture is also proposed. The Folded RNS architecture offers hardware savings of 23–27% for a 40-tap FIR filter and 29–31% for a 60-tap FIR filter. Additionally, it improves speed by 13–15% for a 40-tap FIR filter and 16–19% for a 60-tap folded RNS FIR filter. The implementation of FRM filter bank using the folded FIR filter shows the same trend in hardware saving and speed improvement as in the case of FIR filters. These results demonstrate that the proposed hardware architecture has the potential to improve the efficiency and affordability of DHAs while enhancing the listening comfort, which can enhance the quality of life for patients with hearing impairments.

Efficient Sign-Detection-Scheme Using Modular Computation Technique for the Moduli Set {2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>+1, 2<sup>(n+1)</sup>-1, 2<sup>2n</sup>-5}

In computer arithmetic, one of the most important things to consider in hardware design is the ability of the system to detect and display numbers with their signs. This when properly managed will reduce errors and ensure hardware reliability. But interestingly, detecting and knowing the sign of a residue number during arithmetic operation is very difficult. Magnitude Comparison, Scaling and Number conversions are some of the other difficult operations in Residue Number System (RNS). Unlike the weighted number system, it is even extremely difficult to determine the sign of a number in an RNS architecture thereby hampering the full implementation RNS in general purpose computing. In this paper, an efficient sign detection algorithm for detecting the sign of a number in an RNS architecture is presented. In formulating the algorithms, X maximum, (X_max) is computed from the Dynamic Range, M=∏^k_i=1(m_i). Modular Computation Technique is employed as a converter to compute X from the residues (r₁, r₂, r₃) with respect to a given moduli set, say S= {m₁, m₂ ..., m_n}. X is positive if X-X_max<0 otherwise X is negative and the actual value is this case is computed as X-M. The moduli set {2ⁿ-1, 2ⁿ, 2ⁿ+1, 2⁽ⁿ⁺¹⁾-1, 2²ⁿ-5} is used for the system design implementation and for numerical illustrations. It is observed that the scheme effectively detects the sign of RNS numbers and theoretical analysis showed that simple hardware resources and low-power modular adders are used in the design. It is also observed that the scheme when implemented practically can help project RNS to be used in general purpose computing.

Performance analysis of Low energy and highspeed DA-RNS based FIR filter design for SDR Applications on FPGA

For different applications, the Finite Impulse Response (FIR) filter is widely used in digital signal processing (DSP) applications. We exhibit a significant Residue Number System (RNS)-based FIR filter design for Software Defined Radio (SDR) filtration in this article. Including its underlying concurrency and information clustering process, the RNS provides important statistics over FIR application in specific. According to several residue computing and reverse translation, expanded bit size results in a significant performance trade-off, conversely. Through RNS replication, accompanied by conditional delay optimized reverse processing to minimize the FIR filter trade-off features with filter duration optimized Residue Number System arithmetic is proposed in this study, which involves distributed arithmetic-based residue processing. To execute the task of reverse translation and to store pre-computational properties, the suggested Residue Number System architecture makes use of built-in RAM blocks found in field-programmable gate array (FPGA) devices. The proposed FIR filter with core optimized RNS has the benefit of lowering processing latency delay while rising performance torque. Followed by FPGA hardware synthesis for different input word sizes and FIR lengths verification by the efficiency of the FIR filter core, fetal audio signal detection is performed first. The test results reveal that over the optimization procedure RNS method, a compromise in traditional RNS FIR over filter size is narrowed, as well as a substantial decrease in sophistication.

Residue Number System Fade Mitigation Technique with Error Detection and Correction on a Satellite Communication Link

Rain fade is the loss of signal power at the receiver of a telecommunication system mainly due to absorption and scattering caused by rain in the transmission medium, especially at frequencies above 10 GHz. In order to combat the loss of the signal power at the receiver, there is the need to employ rain fade mitigation techniques. Consequently, researchers have been studying how rain affects the signal in different geographical locations as well as proposing some mitigation techniques. Power control is one of the mitigation techniques that have been proposed. But this technique has some associated challenges. Increasing the power will lead to an increase in cost of transmission which will eventually be passed on to the consumer thereby making satellite services expensive. It requires high power in uplink and downlink which increases the burden either on user terminal or satellite payload. Also, because of health concerns there is a limit to the amount of power that can be radiated to the ground and this is governed by international agreements. Another power management drawback in using this technique is that, uplink power control is not efficient in directing the added power to only the ground station experiencing path attenuation, because the additional power is distributed to all locations within the satellite antenna coverage area. In this paper, we address the power control challenges, by leveraging on the inherent properties of Residue Number System (RNS) and Redundant Residue Number System (RRNS) to propose an RNS architecture using the moduli set {2²ⁿ⁺¹-1, 2²ⁿ -1, 2²ⁿ, 2⁴ⁿ⁺¹ -1, 2²ⁿ +1} that can mitigate rain fade in the satellite link as well as detect and correct multiple errors. In digital communication systems, the bit energy, e_b, is the most important parameter in determining the communications link performance. Numerical analysis shows that the proposed scheme performs better than the traditional method as indicated in the high energy per bit value obtained in the proposed system in comparison with the traditional method, all other things being equal.

Rain Fade Mitigation Technique Using Residue Number System Architecture on KU Band Satellite Communication Link

Rain fade is the loss of signal power at the receiver of a telecommunication system mainly due to absorption and scattering caused by rain in the transmission medium, especially at frequencies above 10 GHz. In order to combat the loss of the signal power at the receiver, there is the need to employ rain fade mitigation techniques. Consequently, researchers have been studying how rain affects the signal in different geographical locations as well as proposing some mitigation techniques. Power control is one of the mitigation techniques that have been proposed. But this technique has some associated challenges. Increasing the power will lead to an increase in cost of transmission which will eventually be passed on to the consumer thereby making satellite services expensive. It introduces a delay in compensation due to link estimation and coordination. Also, because of health concerns there is a limit to the amount of power that can be radiated to the ground and this is governed by international agreements. Another power management drawback in using this technique is that, it is essential to track the power continuously to ensure that the power values are not set too high, which can lead to the front end of the receiver being overdriven and eventually leading to a shutdown or physical damage. In this paper, we address the power control challenges, by leveraging on the inherent properties of Residue Number System (RNS) to propose an RNS architecture using the moduli set {2²ⁿ⁺¹-1, 2²ⁿ -1, 2²ⁿ} that can mitigate rain fade in the satellite link. In digital communication systems, the bit energy, e_b, is the most important parameter in determining the communications link performance. Numerical analysis shows that the proposed scheme performs better than the traditional method as indicated in the high energy per bit value obtained in the proposed system in comparison with the traditional method.

A note on RNS architectures for the implementation of the diagonal function

This paper focuses on some considerations on the diagonal function and its applications to implement non-modular operations like magnitude comparison and sign detection in residue number system (RNS), recently proposed in the literature. According to our results, any implementation involving the diagonal function proposed to date results in excessive hardware overhead and delay, which make it impractical from the application point of view, so that it cannot compete with more traditional approaches.

Randomised multi‐modulo residue number system architecture for double‐and‐add to prevent power analysis side channel attacks

Security in embedded systems is of critical importance since most of our secure transactions are currently made via credit cards or mobile phones. Power analysis-based side channel attacks have been proved as the most successful attacks on embedded systems to retrieve secret keys, allowing impersonation and theft. State-of-the-art solutions for such attacks on public key cryptographic algorithms, such as elliptic curve cryptography, mostly in software, hinder performance and repeatedly attacked using improved techniques. To protect these public key ciphers from both simple power analysis and differential power analysis, as a hardware solution, we propose to take advantage of the inherent parallelisation capability in multi-modulo residue number systems (RNS) architectures to obfuscate the secure information. Random selection of moduli is proposed to randomly choose the moduli sets for each key bit operation. This solution allows us to prevent power analysis, although still providing all the benefits of RNS. In this study, the authors show that differential power analysis, cross correlation analysis and correlation power analysis for a simple binary double-and-add operation are thwarted using their solution.

FIR Filter Implementation Based on the RNS with Diminished-1 Encoded Channel

A technique, based on the residue number system (RNS) with diminished-1 encoded channel, has being used for implementing a finite impulse response (FIR) digital filter. The proposed RNS architecture of the filter consists of three main blocks: forward and reverse converter and arithmetic processor for each channel. Architecture for residue to binary (reverse) convertor with diminished-1 encoded channel has been proposed. Besides, for all RNS channels, the systolic design is used for the efficient realization of FIR filter. A numerical example illustrates the principles of diminished-1 residue arithmetic, signal processing, and decoding for FIR filters.

FIR Filter Implementation Based on the RNS with Diminished-1 Encoded Channel

A technique, based on the residue number system (RNS) with diminished-1 encoded channel, has being used for implementing a finite impulse response (FIR) digital filter. The proposed RNS architecture of the filter consists of three main blocks: forward and reverse converter and arithmetic processor for each channel. Architecture for residue to binary (reverse) convertor with diminished-1 encoded channel has been proposed. Besides, for all RNS channels, the systolic design is used for the efficient realization of FIR filter. A numerical example illustrates the principles of diminished-1 residue arithmetic, signal processing, and decoding for FIR filters.

An RNS Architecture for Quasi-Chaotic Oscillators

Wideband chaotic carrier is a promising solution for wideband communication, since it overcomes the disadvantages of both narrowband and spread-spectrum communication. It is particularly suited to realize information encryption for secure communication. Chaotic signals can be generated by using discrete-time non-linear dynamical circuits, since they can exhibit a quasi-chaotic (QC) behavior. A particular implementation of QC digital filters can be based on finite precision arithmetic and, in particular, on residue number system (RNS) circuits, which possess very attractive features with regard to their VLSI implementation. In the present paper, we propose an RNS architecture that can be used in connection with secure communication. Each RNS channel consists of a QC oscillator, having its coefficients belonging to a Galois field defined by a prime modulus. In particular, the QC behavior is ensured by well-known properties of primitive polynomials in this field, which generate the characteristic feedback of the oscillator. We demonstrate in the paper that the proposed RNS architecture yields a cost-effective VLSI implementation, which favorably compares with respect to other secure communication approaches proposed in the technical literature. We obtain encouraging results both in terms of confidentiality of the encrypted information and of throughput rate for real-time applications. Moreover, we propose an extended architecture suited to the protection of the secure communication system against transmission errors, by using the self-correcting ability of Redundant RNS (RRNS).

RNS architectures for the implementation of the `diagonal function'

The `diagonal function' is a new tool for performing non-modular operations in the Residue Number System (RNS). It is defined from the RNS to the integers and exploits the geometrical disposal in multi-dimensional discrete spaces of integers in residue representations. This paper presents a new class of RNS architectures for the effective implementation of the `diagonal function'. The architectures are general, since they do not impose constraints on the set of moduli, and flexible, since they can be best suited depending on specific system requirements. The superiority of the new architectures with respect to traditional approaches is shown in terms of waste of hardware and time delay.

Novel high-radix residue number system architectures

Novel radix-r modulo-r/sup n/ arithmetic units for residue number system (RNS)-based architectures are introduced in this paper. The proposed circuits are shown to require several times less area than previously reported architectures for particular moduli of operation, while also being preferable in the area/spl times/time complexity sense. The complexity reduction is achieved by extending the carry-ignore property of modulo-2/sup n/ operations to radices higher than two, which are not powers of two. The carry-ignore property is efficiently exploited by introducing simplified digit adders, instead of general radix-r adders. The proposed simplification of digit adders is possible, since the maximum values of certain intermediate digits produced in the architecture are found to be less than r-1. Detailed area and time complexity models are derived for the arithmetic units. The proposed radix-r architectures include multipliers, adders, and merged multipliers-adders. In addition, efficient radix-r binary-to-residue and residue-to-binary conversion techniques and architectures are introduced.

Improved mixed-radix conversion for residue number system architectures

Processor architectures, based on arithmetic cells using residue number systems, are inherently parallel, modular and fault isolating. The fundamental characteristic of a residue number system is its being an unweighted numbering system. The paper describes an improved technique for transforming a residue number into a mixed-radix weighted representation. The proposed conversion algorithm is based on the cyclic patterns inherent in residue number systems. The mixed-radix digits of the proposed conversion procedure are factorised into a product of two terms each; one term is invariant and predetermined, whereas the other is variable and depends upon the particular residue number being converted. In comparison with existing conversion techniques, the proposed conversion method achieves a considerable reduction in the number of arithmetic multiplications needed during the conversion process.

Lower bounds for VLSI implementation of residue number system architectures

Since the number of components that can fit on a single chip is large and rapidly growing, the asymptotic analysis and computational complexity have become applicable to the VLSI systems. We propose a model of computation devoted to VLSI structures based on Residue Number System (RNS). The developed model employs the ‘cut theorem’ which has been used by most of the abstract VLSI models. It is not as general as other reported models, but it gives tighter lower bounds and more accurate measures of performance for RNS structures. This computational model relates the area and time complexities with the inherent properties of RNS, the moduli size and the dynamic range. The model supports the look-up table implementation approach and it is technology-independent.

A VLSI model for residue number system architectures

Combining the Residue Number System as a computational tool and VLSI as a fabrication medium promises to provide modular and cost efficient implementation of many digital signal processing algorithms. In this paper, a memory model has been developed. It is a low level model, which is used to derive relationships between the size of each modulus (in the chosen number system), and both chip area and time required for implementing the corresponding look-up tables. The memory model allows the selection of the most efficient layout for memories which do not have power of two dimensions. A set of multi-look-up table modules has been proposed as building block units for implementing digital signal processing algorithms. A procedure has been developed to optimize the area and time of those modules.