High Volume Manufacturing Requirements Research Articles

Recent Status of the Stochastic Issues of Photoresist Materials in EUV Lithography

In 2019, finally, extreme ultraviolet (EUV) lithography has been applied to high volume manufacturing (HVM) for preparing advanced semiconductor devices. That was very important year for EUV enthusiasts and semiconductor industry. Because it takes for a long time, more than 30 years, to study EUV lithography for realizing HVM. With recent rapid progress on the source power improvement, EUV lithography development including photoresist materials has been achieved HVM requirements. However, the performance of EUV resist materials are still not enough for the expected HVM requirements, even by using the latest qualifying EUV resist materials. One of the critical issues is the stochastic issues, which will be become ‘defectivity’, like a nano-bridge or a nano-pinching. The analyzing summary of the stochastic factors in EUV lithography, and their improvement status are described in this paper. 2 (two) major stochastic issues, which are photon stochastic and chemical stochastic, were observed in the lithography steps. And the improvement status of each stochastic issues including lithographic results are also described.

High-Volume Testing and DC Offset Trimming Technique of On-Die Bandgap Voltage Reference for SOCs and Microprocessors

Since the VLSI chips were invented, as predicted by Moore’s law, the performance, the power, and the cost of the VLSI chips have been improved, which brought a significant benefit to the economy. However, some of the analog circuits do not get a full benefit from the scaling, due to the increased device variability with transistors in smaller dimension. Under such circumstance, the calibration and trimming techniques are essential to overcome the sensitivity to the process variation. This paper presents the trimming technique to correct the direct current (dc) offset error of the bandgap voltage reference circuit, which complies with the high-volume manufacturing (HVM) requirements. The proposed trimming method consists of the combination of two different sequences, the coarse and fine trimming. The accuracy of the dc offset trimming is evaluated by the newly invented method that complies with the HVM requirements. With a compact silicon area of only 700 $\mu \text{m}^{2}$ , the dc offset trimming circuit achieved an accuracy of ±5 mV ( $4\sigma$ ) as a result of the coarse and fine trimming operations.

Cost-effective near-perfect absorber at visible frequency based on homogenous meta-surface nickel with two-dimension cylinder array.

To date, near-perfect light absorbers at visible frequency are still severely impeded by the complicated architecture design and time-consuming costly fabrication procedures. In this work, we design and fabricate a new cost-effective near-perfect absorber at visible frequency based on homogenous meta-surface nickel (Ni) with a two-dimension cylinder array. The simulated and measured average absorption at normal incidence are beyond 94% and 92% over the entire visible wavelength band from 400 nm to 700 nm, respectively. Additionally, the absorbance property was well retained, and the absorptivity still remained beyond 70% when the incident angles vary from 0° to 60°. Our theoretically and experimentally results indicate that the broadband wide-angular absorption can be ascribed to the Rayleigh-Wood anomaly combined with slot modes induced by excited surface plasmon polaritons. Moreover, the low-cost double-beam interference lithography followed by soft nano-imprinting and electroforming technology, which are directly compatible with the cost-effective and high volume manufacturing requirements, are employed to fabricate the proposed absorber. The proposed approach is simple and inexpensive and the obtained ultrathin homogenous meta-surface nickel absorber can be rolled or folded on the surface of various optoelectronics, such as solar system and radiation thermal devices.

(Invited) Next Generation CMOS Devices: Transistor Module Challenges and Opportunities

In this presentation, we first review the overall trends for advanced CMOS devices in terms of scalability and performance. To carry on Moore’s law, devices need to be scaled from node to node. To enable this scaling, taller, more rectangular FinFETs with narrower body width at scaled pitches has been demonstrated. However this leads to several key process and integration challenges such as Fin integrity, capacitance increase, channel mobility, sub-fin isolation, and sidewall doping as well as contact resistance reduction. Next, we review the challenges of increasing FinFET device performance (e.g., mobility boost, Rexternal reduction) such as fin smoothing, epi Source Drain proximity or contact resistance reduction. Regarding alternate channel material, SiGe p-channel FinFET has gained quite a lot of attention in the past several years. Several SiGe integration approaches have been reported in the literature and will be briefly discussed. Consideration of the entire process flow is critical to ensure maximum strain is achieved in the channel with very low defectivity – two critical requirements for High Volume Manufacturing of high performance, low power devices. These topics will be explored for several of the integration approaches mentioned above. Finally, we will discuss the potentially disruptive transition to new device architecture – the Gate-All-Around (GAA) transistor - and discuss process requirements and challenges for this novel device type.

(Invited) Group IV Epitaxy Applications for Enabling Advanced Device Scaling

In the past decade, the surge of demand for mobile devices has been tremendous, and has been a key growth engine for the semiconductor market. These novel devices have all capabilities for sophisticated mobile communication, as well as capabilities for gaming, computing, etc. To address the stringent requirements in terms of battery lifetime, device speed, and scaling, the design and manufacturing processes of mobile devices needs constant innovation. Historically, Group IV epitaxial processes such as e-SiGe source/drain have played a critical role in meeting the needs for device scaling and performance in planar devices. One dramatic change that has taken place to address device scalability is the move to the multigate architecture of the FinFET (Fin Field Effect Transistor), which enables the virtual increase of the gate length and dramatically improved electrostatic performance. Beyond FinFET, the GAA (Gate All around Transistors) device structure is one of the most promising paths for offering another disruptive leap in device scaling. This paper discusses the increasingly critical role of epitaxy applications for enabling both of these new device architectures, which have much more complex integration schemes and tighter process control requirements than planar devices. We first review the overall trends for advanced CMOS devices in terms of scalability and performance. To carry on Moore’s law, devices need to be scaled from node to node. To enable this scaling, taller, more rectangular FinFETs with narrower body width at scaled pitches has been demonstrated. However this leads to several key process and integration challenges such as Fin integrity, capacitance increase, Channel mobility, sub-fin isolation, sidewall doping as well as contact resistance reduction. Next, we review the challenges of increasing FinFET device performance (e.g., mobility boost) by using SiGe p-channel FinFET, which has gained quite a lot of attention in the past several years. Several SiGe integration approaches have been reported in the literature, all which are enabled by new epitaxy applications. Examples of these SiGe channel integration approaches include SiGe replacement channel, STI last SiGe formation, cladded SiGe and SiGe condensation. There are significant integration challenges for each of these approaches from the perspective of epitaxial growth and related processes. For example, each of SiGe channel formation schemes have some specific requirements not only on the pre-clean and/or epi growth but also on the overall CMOS integration scheme (alleviation of SiGe oxidation, recess, Fin shaping, junction formation etc.). Consideration of the entire process flow is critical to ensure maximum strain is achieved in the channel with very low defectivity – two critical requirements for High Volume Manufacturing of high performance, low power devices. These topics will be explored in detail for several of the integration approaches mentioned above. Finally, we will discuss the potentially disruptive transition to a new device architecture – the Gate-All-Around (GAA) transistor - and discuss new epitaxy opportunities, requirements and challenges for this new device type.

(Invited) Group IV Epitaxy Applications for Enabling Advanced Device Scaling

In this paper, we first review the overall trends for advanced CMOS devices in terms of scalability and performance. To carry on Moore’s law, devices need to be scaled from node to node. To enable this scaling, taller, more rectangular FinFETs with narrower body width at scaled pitches has been demonstrated. However this leads to several key process and integration challenges such as Fin integrity, capacitance increase, channel mobility, sub-fin isolation, and sidewall doping as well as contact resistance reduction. Next, we review the challenges of increasing FinFET device performance (e.g., mobility boost) by using SiGe p-channel FinFET, which has gained quite a lot of attention in the past several years. Several SiGe integration approaches have been reported in the literature, all which are enabled by new epitaxy applications. Consideration of the entire process flow is critical to ensure maximum strain is achieved in the channel with very low defectivity – two critical requirements for High Volume Manufacturing of high performance, low power devices. These topics will be explored for several of the integration approaches mentioned above. Finally, we will discuss the potentially disruptive transition to new device architecture – the Gate-All-Around (GAA) transistor - and discuss new epitaxy opportunities, requirements and challenges for this new device type.

Extending the path for efficient extreme ultraviolet sources for advanced nanolithography

Developing efficient light sources for extreme ultraviolet (EUV) lithography is one of the most important problems of high volume manufacturing (HVM) of the next generation computer chips. Critical components of this technology are continued to face challenges in the demanding performance for HVM. Current investigations of EUV and beyond EUV (BEUV) community are focused on the dual-pulse laser produced plasma (LPP) using droplets of mass-limited targets. Two main objectives as well as challenges in the optimization of these light sources are related to enhancement of the conversion efficiency (CE) of the source and increase components lifetime of the collector optical system. These require significant experimental and computer simulation efforts. These requirements call for fine detail analysis of various plasma physics processes involved in laser target interactions and their effects on source optimization. We continued to enhance our comprehensive HEIGHTS simulation package and upgrade our CMUXE laboratories to study and optimize the efficiency of LPP sources. Integrated modeling and experimental research were done to both benchmark simulation results and to make projections and realistic predictions of the development path for powerful EUVL devices for HVM requirements. We continued the detail analysis of dual-pulse laser systems using various laser wavelengths and delay times between the two pulses. We showed that the efficiency of EUV sources can be improved utilizing the higher harmonics of Nd:YAG laser for the prepulse and the first harmonics for the main pulse, while still having lower efficiency than the combination involving CO2 laser in the range of parameters studied in this case. The differences in optimization process as well as in the source characteristics for two combinations of laser wavelengths were analyzed based on details of atomic and hydrodynamics processes during the evolving plasma plumes.

The role of plasma evolution and photon transport in optimizing future advanced lithography sources

Laser produced plasma (LPP) sources for extreme ultraviolet (EUV) photons are currently based on using small liquid tin droplets as target that has many advantages including generation of stable continuous targets at high repetition rate, larger photons collection angle, and reduced contamination and damage to the optical mirror collection system from plasma debris and energetic particles. The ideal target is to generate a source of maximum EUV radiation output and collection in the 13.5 nm range with minimum atomic debris. Based on recent experimental results and our modeling predictions, the smallest efficient droplets are of diameters in the range of 20–30 μm in LPP devices with dual-beam technique. Such devices can produce EUV sources with conversion efficiency around 3% and with collected EUV power of 190 W or more that can satisfy current requirements for high volume manufacturing. One of the most important characteristics of these devices is in the low amount of atomic debris produced due to the small initial mass of droplets and the significant vaporization rate during the pre-pulse stage. In this study, we analyzed in detail plasma evolution processes in LPP systems using small spherical tin targets to predict the optimum droplet size yielding maximum EUV output. We identified several important processes during laser-plasma interaction that can affect conditions for optimum EUV photons generation and collection. The importance and accurate description of modeling these physical processes increase with the decrease in target size and its simulation domain.

Cleaning of step-and-flash imprint masks with damage-free nonacid technology

Step-and-flash imprint lithography (S-FIL®) is a promising lithography strategy for semiconductor manufacturing at device nodes below 32 nm. The S-FIL 1:1 pattern transfer technology utilizes a field-by-field ink jet dispense of a low-viscosity liquid resist to fill the relief pattern of the device layer etched into the glass mask. Compared to other sub-40-nm critical dimension (CD) lithography methods, the resulting high resolution, high throughput through clustering, 3-D patterning capability, low process complexity, and low cost of ownership of S-FIL makes it a widely accepted technology for patterned media as well as a promising mainstream option for future CMOS applications. Preservation of mask cleanliness is essential to avoid the risk of repeated printing of defects. The development of mask cleaning processes capable of removing particles adhered to the mask surface without damaging the mask is critical to meet high-volume manufacturing requirements. We present various methods of residual (cross-linked) resist removal and final imprint mask cleaning. Conventional and nonconventional (acid-free) methods of particle removal are compared and the effect of mask cleaning on pattern damage and CD integrity is also studied.

Aerosol Jet® Material Deposition for High Resolution Printed Electronic Applications

Aerosol Jet printing, is finding wide use in a number of electronic manufacturing applications. The Aerosol Jet systems deposit a wide variety of functional materials onto a wide variety of substrates without conventional masks or thin-film equipment. The process is non-contact, enabling traces to be printed over steps or curved surfaces. Printed features can be from less than 10 microns to several centimeters, with thicknesses from 10's of nanometers to 10's of microns. The Aerosol Jet process utilizes both low viscosity inks and diluted pastes for an operating range of approximately 1-1000cP. Typical materials that can be printed include nanoparticle metal suspensions, polymers and adhesives. Conductor traces can be printed using gold, silver or other nanoparticle inks. Conductors can also be formed by printing a seed layer, followed by electroless plating. Polymer thick film pastes can be printed to form embedded resistors. Polyimide and various epoxies can be printed for adhesives, overcoat dielectrics, etc. The system also supports deposition of semiconducting inks, carbon nanotubes (CNTs) and biomaterials. The Aerosol Jet process is compatible with a wide variety of substrates, including silicon, polyimide, glass, FR-4 and aluminum oxide. In principle, virtually any substrate can be used provided that the ink is compatible with the substrate. Applications for the Aerosol Jet technology include flexible displays, touchscreens, fuel cells, high efficiency solar cells, 3-dimensional interconnects, and embedded components including sensors, resistors, and antennae. Aerosol Jet has distinct functional and cost advantages over traditional methods such as screenprinting, lithography and wirebonding. The solution also compares well versus InkJet printing, especially in meeting high-volume manufacturing requirements. The Aerosol Jet process is compatible with a variety of substrates, including silicon, polyimide, glass, FR-4 and aluminum oxide. In principle, virtually any substrate can be used provided that the ink is compatible with the substrate. Applications for the Aerosol Jet technology include flexible displays, EMI shielding, solder-free electronics, high efficiency solar cells, 3-dimensional interconnects, and embedded components including sensors, resistors, and antennae.

Cell Broadband Engine processor: Design and implementation

The Cell Broadband Engine™ (Cell/B.E.) processor was developed by Sony, Toshiba, and IBM engineers to deliver a high-speed, high-performance, multicore processor that brings supercomputer performance via a custom system-on-a-chip (SoC) implementation. To achieve its goals, the Cell/B.E. processor uses an innovative architecture, new circuit design styles, and hierarchical integration and verification techniques. The Cell/B.E. processor design point was also targeted at high-volume manufacturing. To meet high-volume manufacturing requirements, the chip was designed so that it could be completely tested in less than 26 seconds. In addition to the above items, the Cell/B.E. processor was designed with the “triple design constraints” of maximizing performance while minimizing area and power consumed. The initial application was targeted at real-time systems that require high-speed data movement for both on-chip and off-chip transfers. This application also required very high speed compute and real-time response processes.

Predicting the thermomechanical distortion of extreme ultraviolet lithography reticles for preproduction and production exposure tools

The thermomechanical distortion of extreme ultraviolet lithography (EUVL) reticles during exposure may lead to significant image placement (IP) errors. As throughput requirements for high-volume manufacturing (HVM) increase, the necessary illumination power levels rise, resulting in further distortion of the reticle. The thermal response of the EUVL reticle is predicted using finite element models for a typical HVM exposure tool. The effect of increasing the EUV source power on reticle heating is investigated by comparing the thermal distortion expected in exposure tools using different throughput values corresponding to the α tool, β tool, and the HVM exposure tool (γ tool). The effect of imperfect contact between the EUVL reticle and the chuck surface on the IP errors due to thermal distortion is studied for different effective contact area ratios. Also, an alternative design concept is proposed, aimed at providing a solution to the microparticle trapping problem (between the reticle and the chuck).

Characterization of micromechanical structures using white-light interferometry

As microelectromechanical systems (MEMS) move rapidly towardscommercialization, the issue of mechanical characterization has emerged as amajor consideration in device design and fabrication. It is now common to includea set of test structures on a MEMS wafer for extraction of thin film materialproperties (in particular, residual stress, stress gradient and Young’s modulus),and for process and device monitoring. These structures usually consist ofmicromachined beams and strain gauges. Measurement techniques include tensiletesting, scanning electron microscopy (SEM) imaging, atomic force microscopy(AFM) analysis, surface profiling and Raman spectroscopy. However, these testsare often destructive and may be difficult to carry out at the wafer scale.Instead of these methods, this paper uses white-light interferometry surfaceprofiling for material characterization and device inspection. Interferometryis quick, non-destructive, non-contact, and can offer a high densitylateral resolution with extremely high sensitivities to the surface in thez-direction—allessential requirements for high volume manufacturing. A range of devices isemployed to illustrate the capabilities of white-light interferometry as ameasurement and process characterization tool.It is shown that residual stressmay be determined by using electrostatic actuation to pull fixed–fixed beamstowards the substrate, and interferometry to record the beam deflection profile.Finite-element simulation software is employed to model this deflection, and toestimate the material properties which minimize the difference between themeasured and simulated profiles. The results agree well with blanket filmmeasurements.