Reliability Screen Research Articles

Oseltamivir for influenza in adults and children: systematic review of clinical study reports and summary of regulatory comments

Objective To describe the potential benefits and harms of oseltamivir by reviewing all clinical study reports (or similar document when no clinical study report exists) of randomised placebo controlled trials...

(Invited) (ECS Electronics & Photonics Division Award )Wafer-Level Step-Stressing of InGaP/GaAs HBTs

Wafer-level step-stress experiments on high voltage Npn InGaP/GaAs HBTs are presented. A methodology utilizing brief, monotonically increasing stresses and periodic, interrupted parametric characterization is presented. The method and various examples of step-stressed HBTs illustrate the value of the technique for screening the reliability of HBT wafers. Degradation modes observed in these InGaP/GaAs HBTs closely correspond to a subset of those in other, longer types of reliability experiments and can be relevant in a reliability screen. A statistical sampling of HBT wafers reveals a consistently realized critical destructive limit over a very narrow power range, which indicates that thermal stress is the main cause of degradation. When stepped just shy of the destructive limit, electrical characteristics are capable of revealing gradual degradation. The end state of stressing typically involves shorting of both the base-emitter and base-collector junctions. Interrupted characterization revealed cases where base-emitter shorts preceded base-collector shorts and other cases where base-collector shorts occurred first. Examples of degradation include reductions in reverse breakdown voltage, increases in the offset voltage, and drops in current gain. These wafer-level step-stress techniques show promise for reducing the large time lag between wafer fabrication and useful reliability screening in HBTs.

Optimization of silicon technology for the IBM System z9

IBM 90-nm silicon-on-insulator (SOI) technology was used for the key chips in the System z9TM processor chipset. Along with system design, optimization of some critical features of this technology enabled the z9TM to achieve double the system performance of the previous generation. These technology improvements included logic and SRAM FET optimization, mask fabrication, lithography and wafer processing, and interconnect technology. Reliability improvements such as SRAM optimization and burn-in reliability screen are also described.

Defect Detection Using Quiescent Signal Analysis

IDDQ or steady state current testing has been extensively used in the industry as a mainstream defect detection and reliability screen. The background leakage current has increased significantly with the advent of ultra deep submicron technologies. This increased background leakage noise makes it difficult to differentiate defect-free devices from those with defects that draw significantly small amount of currents. Therefore it is impossible to use single threshold IDDQ testing for today’s technologies. Several techniques that improve the resolution of IDDQ testing have been proposed to replace the single threshold detection scheme. However, even these techniques are suffering from loss of resolution that is required for detection of subtle defects in the presence of leakage currents in excess of a few mA. All these techniques use a single IDDQ measurement for detection and thus the scalability of these techniques is limited. Quiescent Signal Analysis (QSA) is a novel IDDQ defect detection and diagnosis technique that uses IDDQ measurements at multiple chip supply pads. Implicit in our methodology is a leakage calibration technique that scales the total leakage current over multiple simultaneous measurements. This helps in decreasing the background leakage component in individual measurements and thus increases the resolution of this technique to subtle defects. Defect detection is accomplished by applying linear regression analysis to the multiple supply port measurements and using outlier analysis to identify defective devices. The effectiveness of this technique is demonstrated in this paper using simulation experiments on portion of a production power grid. Predicted chip size and leakage values from the International Technology Roadmap for semiconductors (ITRS) are used in these experiments. One of the other major concerns expressed in ITRS is that of significant increase in intra-die process variations. The performance of the proposed technique in presence of such variations is evaluated using three different intra-die process variation distribution models.

An application of an artificial neural network to reliability screen classification from noise measurement

In this paper, we suggest that the reliability screen classification of BJTs from noise measurement belongs in statistical pattern recognition, then the multilayer artificial neural network is used as reliability screen classifier. The structure of a multilayer neural network (MLNN) with a back-propagation algorithm for training weights of the MLNN is discussed. This method can obtain optimal decision regions and the minimum summed squared error. Finally, an application of a neural network to the reliability screen classification of 100 BJTs is given, the results show that the MLNN is a feasible reliability screen classifier.

Optimal low-frequency noise criteria used as a reliability test for BJTs and experimental results

Two basic problems in the application of noise criteria to reliability testing are considered. First, the need to look at all noise mechanisms rather than noise at a specific frequency is emphasized, and noise criteria using both 1 f noise and g− r noise are established. Second, the physical mechanisms which explain the low noise level of some failed devices are discussed, and the optimal noise threshold levels are found for minimum error during reliability testing. Reliability testing results for 1000 BJTs (3DG6) show that the failure rate of devices which initially exhibit high noise is about 2–3 times higher than for devices which initially have low noise. This means that the life expectancy of BJTs with a low noise level (using optimal noise criteria) is increased by a factor of 1.5–2.5; thus, noise measurements could be a useful reliability screen classification method for BJTs.

How parts fail: A fundamental explanation for any part failure exists, and it's up to the failure analyst to find the cause with modern sleuthing

Gives an understanding of how semiconductor and other electronic parts fail is essential to improving the reliability of devices as well as that of the systems in which they are used. Such failure analyses help identify device failure modes, mechanisms, and stress factors that influence degradation. A device can fail in a catastrophic, degradation, or intermittent mode. Electrical failures are usually opens, shorts, or parameters out of specification. The failure mechanism is the basic chemical or physical change that results in an identifiable failure mode. Parts failures can be labeled as early fallout , stress-related, and wearout. Early failures are often linked to design and manufacturing flaws or to reliability screen test escapes but can be stress-related. Normal operating stresses cause most failures that occur after the early ones. Wearout failures are linked to aging and deterioration.