Reliability Of Wafer-level Package Research Articles

Thermal-mechanical reliability analysis of WLP with fine-pitch copper post bumps

PurposeThis study aims to investigate the several parameters in wafer-level packaging (WLP) to find the most critical factor impacting the thermal fatigue life, such as the height of copper post, the height of solder bump, the thickness of chip. The FEA results indicate the height of solder bumps is the most important factor in the whole structure.Design/methodology/approachThe copper post bumps with 65 µm pitch are proposed to investigate the thermal-mechanical performance of WLP. The thermal cycle simulation is used to evaluate the reliability of WLP by using finite element analysis (FEA). Taguchi method is adopted to obtain the sensitivity of parameters of three-dimension finite element model, for an optimized configuration.FindingsIt can be found that the optimal design has increased thermal fatigue life by 147% compared with the original one.Originality/valueIt is concluded that the finite element simulation results show outstanding thermal-mechanical performances of the proposed 65 µm pitch copper post bumps of WLP, including low plastic strain, high thermal fatigue life, which are desired for mobile device.

Effect of Different PBO-Based RDL Structures on Chip-Package Interaction Reliability of Wafer Level Package

In this paper, CPI (chip-package interaction) reliability of WLP (wafer level package) was investigated. PBO (Polybenzoxazole)-based RDL (redistribution layer) structure was the primary focus. Firstly, the stress distribution for PBO structures was studied by simulation. Secondly, two types of the chip with different PBO structures completed the accelerating experiments. Based on our investigation, the results of CPI reliability tests are coincident with the simulation data. It can be applied to the early prediction for the risk level of CPI reliability. Additionally, failure mechanisms were figured out for different PBO structures. Design A has the potential risk to suffer corrosion damage owing to exposed SR (seal ring) and CAS (crack stop). Design B has a four times failure rate in THT (Temperature and Humidity Test), which related to hotspots around SR. These results suggest that protecting SR and relieving hotspots effect will effectively enhance CPI reliability performance of WLP.

Reliability Assessment of Wafer Level Package using Artificial Neural Network Regression Model

ABSTRACTFor electronic packaging structure, there are many design parameters that will affect its reliability performance, using experimental way to obtain the reliability result will take a considerable amount of time. Therefore, how to shorten the design time becomes a critical issue for new electronic packaging structure development. This research will combine artificial intelligence (AI) and simulation technology to assess the long-term reliability of wafer level packaging (WLP). A simulation technology using finite element method (FEM) with appropriate mechanics theories has been validated by multiple experiments will replace the experiment to create reliability results for different WLP structures. After a big WLP structure-reliability database created, this study will apply artificial neural network (ANN) theory to analyze this database and obtains a regression model for structure-reliability relationship of WLP. Once the regression model is established and validated, the WLP geometry, such as pad size, die and buffer layer thickness, and solder volume, etc. can be simply entered, and then the WLP reliability results can be immediately obtained through the ANN regression model.

Wafer Level Package の接合信頼性に及ぼす材料特性の影響

Wafer Level Package の接合信頼性に及ぼす材料特性の影響

Reliability Assessment of Wafer Level Packages With Novel FeNi Under Bump Metallization

FeNi alloy is considered a possible substitute for Cu as under bump metallization (UBM) in wafer level package (WLP) since it forms very thin intermetallic compound (IMC) layer with Pb-free solder in the reflow process. In this paper, WLPs with FeNi and Cu UBM were fabricated and their board level reliabilities were studied comparatively. The WLP samples assembled on the printed circuit board (PCB) were subjected to temperature cycling and drop tests according to JEDEC standards. The results showed that the reliability of WLP with FeNi UBM was a little lower than that with Cu UBM. The main failure modes for both FeNi and Cu UBM samples in temperature cycling test were the crack in IMC or solder ball on PCB side. And detachments between UBM and the redistribution layer (RDL) were also observed in Cu UBM WLPs. In drop test, the crack of RDL was found in all failed FeNi UBM samples and part of Cu UBM ones, and the primary failure mode in Cu UBM samples was the crack of IMC on PCB side. In addition, the finite element analysis (FEA) was carried out to further understand the difference of the failure modes between the FeNi UBM samples and the Cu UBM samples. The high stress was observed around the UBM and the pad on PCB in the temperature cycling model. And the maximum stress appeared on the RDL in the drop simulation, which was obviously larger than that on the pad. The FEA results showed that the introduction of FeNi UBM increased the stress levels both in temperature cycling and drop tests. Thus, the FeNi alloy cannot simply replace Cu as UBM in WLP without further package structural optimization.

Next generation thin film polymers for WLP applications and their mechanical and electrical characterization

Thin film polymers, like PI, PBO and BCB are used in every wafer level packaging device. The improvement of the reliability of wafer-level packages and chip I/Os consider the choice of the polymer, which is used as dielectric on the chip, as a minor point. Because the production lines are normally fixed on one polymer and the high investments to evaluate the processing of an alternative polymer formulation in combination with costly reliability test seems to be not attractive till today. But the increased demands of advanced WLP and 3-D-Integration, which includes thin chips, chips stacking and higher routing densities, leads to reaching the limits of the common used material system combinations. The demand of better polymer films becomes evident by the fact that dozens of “next generation polymers” have entered the marked in the last years, which are tailored to get higher mechanical toughness and electrical performance aside of a nearly unchanged resolution capacity. The challenge for new polymer formulation is the evaluation of the processing and the generation of a reliable material property data base, which set the basics for any benchmarking to the already used polymer materials. The processing evaluation is done typically by the material supplier or the fab himself, where no special equipment is needed. The material property generation is a quite more complex topic because you need special equipment and partly the material need to be free standing without any substrate. This is also a handling issue, if we talk about thin films in the range of 5 to 20μm. This paper presents the reliable thin film polymer properties characterization of mechanical and electrical values. The measurements of the mechanical properties include the estimation of parameters like young's modulus, tensile strength, elongation at break, coefficient of thermal expansion, stress and time-temperature related effects. The evident topic of warpage related impacts by “new generation polymers” will be presented and discussed. Measurement structures on wafer-level are developed for the estimation of the electrical parameters, which allows a high accuracy and a device relevant value estimation. Parameters like break down voltage, leakage current, dielectric constant, loss factor are measured related to frequencies by MIM and resonator structures. We demonstrate with analyzing of the time-dependent dielectric breakdown (TDDB) of thin film polymers that there is an exponential linkage between field strength and the time till the breakthrough occurs. The mechanical and electrical properties were also investigated related to aging effects, when the application is running on elevated temperature. We examine a degradation of the mechanical and electrical performance, which should be taken into account for the mechanical system reliability and also for impedance controlled HF-application. This paper present advanced material characterization of thin film polymers which gives a guideline for the decision of the polymer related to the demands of the application.

Solder Joint Reliability Study for Wafer Level Packages on Flexible and Rigid Boards

Applications of Wafer Level Packages (WLPs) have shown tremendous growth in the rapid developing smartphones and other portable electronic devices. The technology trends lead to smaller chip size, low cost, and more integrated functions, but also face higher reliability requirements due to the reduced number of solder bumps as well as smaller bump size and height. New assembly technologies such as flexible phone board and conformal coating also brought up new thermo-mechanical reliability challenges. Based on 3D finite element modeling, the current studies focus on solder joint reliability of WLPs and compared between flex based and traditional rigid based WLP assemblies. Conformal coated and underfilled WLPs as well as some bump parameters are also studied. The parametric studies were carried out in ANSYS and all models were created by using APDL (ANSYS Parametric Design Language) scripts. Each simulation starts from stress free status set at solder reflow temperature and were subjected to thermal cyclic load between −40 and +125°C with ramp and dwell time. Creep strain was considered for solder alloys and kinematic plastic hardening was considered for other elastic-plastic materials. The solder fatigue life is estimated by using modified Coffin-Manson equation and was compared with available thermal cycling test data. The results show that underfill is still the most effective option and conformal coating can play an important role if the right material is selected. Bump parameters such as height, which have certain effects on the solder reliability on WLP-on-Rigid, have limited impact on WLP-on-Flex assembly.

Multiple impact characterization of wafer level packaging (WLP)

Wafer level packaging (WLP) of connectivity RF components for mobile devices has emerged as a low-cost and high performance, enabling technology. WLP devices are electronic components with an exposed die that utilizes a ball pitch compatible with standard surface mount technology (SMT) equipment and common printed circuit board (PCB) design techniques. WLP allows the devices to be directly mounted to the PCB of portable devices. One concern of adopting WLP for mobile device applications is reliability under multiple dynamic loading conditions, such as phone drop, due to the fragile nature of the exposed silicon die and the unique packaging designs. A series of dynamic 4-point bend tests were conducted to evaluate the multiple impact reliability of WLP samples. The purpose of this work was to better understand the failure modes and actual reliability of WLP under uniaxial loading, which is commonly observed in mobile drop simulations and tests. The results have been applied to WLP failure prediction for the system-level drop test by using simulation technology.

Designing for reliability using a new Wafer Level Package structure

Wafer Level Packages are one of the most advanced packaging concepts. It combines the advantages of flip chip with conventional surface mount technologies. In recent years, we have seen a tremendous growth in the application of Wafer Level Packages, both in quantities as well as in the number of products where they are implemented. The technology is, however, not without it is challenges with 1st and 2nd level reliability issues. For instance, the limit on the size of Wafer Level Packages has to do with the 2nd level, or solder bump, reliability. This paper highlights our major research and development results on understanding and enhancing the 1st and 2nd level reliability of Wafer Level Packages using combined experimental and virtual prototyping (thermal, mechanical and thermo-mechanical) techniques. Typical 1st level reliability problems within Wafer Level Packages are cracking of repassivation materials, fatigue of bond over active pads, and cracks within the Under Bump Metalisation. Typical 2nd level problems concern solder fatigue and brittle fractures within the intermetallics. To investigate the physics of failure for these problems, dedicated parametric finite element models are constructed including the thin IC layers. Two structures are explored to their potential reliability benefits, being the traditionally used repassivation structure and a newly developed Bump on Active structure. This so-called BUMA structure makes use of a thick Al buffer layer. By combining the experimental results with reliability prediction models, both structures in terms of 1st and 2nd level reliability performance are explored. Based on the results we have designed and manufactured an improved construction that significantly outperforms current solutions.

Corrections to "Enhancing the reliability of wafer level packaging by using solder joints layout design"

In the original paper (see ibid., vol.29, no.4, p.877-85, Dec. 2006) the photographs of authors Chang-Ming Liu and Chang-Chun Lee were inadvertently switched in the biography section. The correct placement is shown here.

Enhancing the Reliability of Wafer Level Packaging by Using Solder Joints Layout Design

During the design and manufacturing processes of electronic packaging, solder joints are fabricated using a variety of methods to provide both mechanical and electrical connections for different applications. They include flip chip, wafer level chip scale packaging (WLCSP), fine pitch ball grid array (BGA), and chip scale packaging (CSP). The solder joint shape prediction methods have been incorporated as a design tool to enhance the reliability of the WLCSP. However, the reliability of solder joints for a large chip size such as 10mmtimes10mm without underfill remains questionable. In this research, a hybrid method combining an analytical algorithm with the energy-based approach is applied to predict standoff heights and geometry profiles of the solder joints. In addition, a hybrid-pad-shape system is proposed to design the solder ball layout, and to enhance the reliability of the solder joints. Next, a nonlinear and parametric finite element analysis is conducted to investigate the reliability issues that result from several design parameters. In addition, an experimental validation is completed to verify the correctness and feasibility of the solder joint shape prediction methods and finite element analysis procedures. The design parameters considered in this study include solder joint layout, solder volume, pad diameter, as well as the ratio and orientation of the elliptical pad. With regards to solder joint layout design, the solder joints located in the corner areas can be considered as structural dummy balls with no electrical signals passing through them. The results reveal that when the WLCSP has large round pads, or properly oriented elliptical solder joint pads at the corner areas underneath the chip, then the maximum equivalent plastic strain of the solder joints will be effectively reduced. As a result, the solder joint fatigue life under thermal loading will be greatly enhanced. Furthermore, the findings of this research can be used as a design guideline for electronic packaging with area array interconnections such as CSP, flip chip packaging, Super CSP, and fine pitch BGA

Solder joint reliability of a polymer reinforced wafer level package

Wafer level packages (WLPs) have demonstrated a very clear cost-advantage vs traditional wire-bond technologies, especially for small components that have a high number of dice and I/O per wafer. Ultra CSP ® is a WLP developed by the Kulicke & Soffa Flip Chip Division (formally Flip Chip Technologies). Typical products utilizing the Ultra chip scale package (CSP) have 5×5 or less area arrays at 0.5 mm pitch. This relatively small array has been limited by the inherent solder joint reliability of WLPs. A much larger subset of higher I/O IC’s could benefit from WLPs provided that standard reliability requirements are achieved without the use of underfill. A new polymer reinforcement technology, “Polymer Collar WLP™”, has been developed by K&S Flip Chip Division. Polymer Collar WLP utilizes a polymer reinforcement structure surrounding the solder joint and it has demonstrated more than 50% increase in solder joint life in thermal cycling tests. The most attractive feature of the Polymer Collar WLP process is its simplicity. A simple replacement of the standard solder flux with Polymer Collar material during the solder attach process is all that is required. This simplicity makes Polymer Collar the most cost-effective solution for adding a polymer reinforcement structure to the solder joint. Other methods in use today require additional complex and costly manufacturing steps. This Polymer Collar WLP is expected to widen the WLP market to include larger arrays where the Ultra CSP did not have suitable solder joint reliability.

The Surface Evolver and the stability of liquid surfaces

The Surface Evolver is an interactive program for studying the shapes of liquid surfaces. Recently added features permit the calculation of the Hessian matrix of second derivatives of the energy. The Hessian can be used for fast convergence to an equilibrium, and eigenvalue analysis of the stability of that equilibrium. This paper describes the use of the Hessian by the Surface Evolver, presents some sample stability analyses, and gives some numerical results on the accuracy and convergence of the methods. It is also shown how one can evolve unstable surfaces.