Reliability Analysis Of Logic Circuits Research Articles

Logic Circuits Reliability Analysis using Signal Probability and Bayesian Network Concepts

Background: Reliability analysis of logic circuits has been widely investigated due to increasing fault occurrence in modern integrated circuits. Simulation-based and analytical methods are developed to estimate the reliability of logic circuits. Methods: In this paper, a signal probability-based method is presented to estimate the reliability of logic circuits. In the proposed approach, four signal probabilities (correct 0, correct 1, incorrect 0, and incorrect 1) are derived (for every node of the circuit) using a probabilistic transfer matrix (PTM), and the correlation coefficients (CCs) are deployed to resolve the reconvergent fanouts issues. The CCs are defined in a fanout cone and are propagated through the logic gates to the related reconvergent nodes. The Bayesian network concept is applied to achieve more accuracy in the propagation of CCs through the logic gates. Results: The accuracy and scalability of the proposed method are proved by various simulations on benchmark circuits (ISCAS 85, LGSynth91, and ITC99). The proposed method efficiently solves the reconvergent fanout problem. Moreover, the proposed method outperforms the previous methods regarding accuracy and scalability. Conclusion: Simulation results on ISCAS 85, LGSynth91, and ITC99 benchmark circuits show less than 3% average error compared with the accurate simulation-based fault injection method.

SPLM: A Flexible and Accurate Reliability Assessment Model for Logic Circuits

Reliability evaluation by using probabilistic computational models has become an important research field in modern digital designs. Based on the profound understanding of different reliability evaluation methods, this paper proposes a universal model for signal probability and reliability analysis of logic circuits. The proposed Signal Probability Level Matrix (SPLM) provides us with the reliability and signal probability of the entire circuit as well as individual outputs. We can deal with SPLM very flexibly depending on different applications and design constraints. The accuracy and efficiency of the proposed model have been proved and verified by representative circuits in literatures. Furthermore, the proposed model is particularly useful in reliability assessment in cascade-structure circuits such as ripple carry adders.

Reliability Analysis of Logic Circuits

Reliability of logic circuits is emerging as an important concern in scaled electronic technologies. Reliability analysis of logic circuits is computationally complex because of the exponential number of inputs, combinations, and correlations in gate failures. This paper presents three accurate and scalable algorithms for reliability analysis of logic circuits. The first algorithm, called observability-based reliability analysis, provides a closed-form expression for reliability and is accurate when single gate failures are dominant in a logic circuit. The second algorithm, called single-pass reliability analysis, computes reliability in a single topological walk through the logic circuit. It computes the exact reliability for circuits without reconvergent fan-out, even in the presence of multiple gate failures. The algorithm can also handle circuits with reconvergent fan-out with high accuracy using correlation coefficients as described in this paper. The third algorithm, called maximum- k gate failure reliability analysis, allows a constraint on the maximum number (k) of gates that can fail simultaneously in a logic circuit. Simulation results for several benchmark circuits demonstrate the accuracy, performance, and potential applications of the proposed algorithms.

Probabilistic transfer matrices in symbolic reliability analysis of logic circuits

We propose the probabilistic transfer matrix (PTM) framework to capture nondeterministic behavior in logic circuits. PTMs provide a concise description of both normal and faulty behavior, and are well-suited to reliability and error susceptibility calculations. A few simple composition rules based on connectivity can be used to recursively build larger PTMs (representing entire logic circuits) from smaller gate PTMs. PTMs for gates in series are combined using matrix multiplication, and PTMs for gates in parallel are combined using the tensor product operation. PTMs can accurately calculate joint output probabilities in the presence of reconvergent fanout and inseparable joint input distributions. To improve computational efficiency, we encode PTMs as algebraic decision diagrams (ADDs). We also develop equivalent ADD algorithms for newly defined matrix operations such as eliminate_variables and eliminate_redundant_variables , which aid in the numerical computation of circuit PTMs. We use PTMs to evaluate circuit reliability and derive polynomial approximations for circuit error probabilities in terms of gate error probabilities. PTMs can also analyze the effects of logic and electrical masking on error mitigation. We show that ignoring logic masking can overestimate errors by an order of magnitude. We incorporate electrical masking by computing error attenuation probabilities, based on analytical models, into an extended PTM framework for reliability computation. We further define a susceptibility measure to identify gates whose errors are not well masked. We show that hardening a few gates can significantly improve circuit reliability.

Reliability analysis of logic circuits : P. DesMarais and M. Krieger. Microelectron. Reliab.16, 29 (1977)

Reliability analysis of logic circuits : P. DesMarais and M. Krieger. Microelectron. Reliab.16, 29 (1977)

Reliability analysis of logic circuits

An efficient algorithm is presented for computing the reliability matrix of a logic network whose components are characterized by a known probability of malfunctioning. Using the concept of path sensitizing, a graphical representation of error propagation is derived. Through the computation of Boolean path functions, the information provided by these graphs is put into a malfunction table from which the matrix entries are directly computed. The method not only offers computational efficiency but also provides further physical insight into the reliability problem.

Reliability analysis of logic circuits : P. DesMarais and M. Krieger. IEEE Trans. Reliab.R-24, 46 (1975)

Reliability analysis of logic circuits : P. DesMarais and M. Krieger. IEEE Trans. Reliab.R-24, 46 (1975)