Regulated Cascode Current Mirror Research Articles

A Modified Current-Mode VCSEL Driver for Short-Range LiDAR Sensor Applications in 180 nm CMOS

This paper presents a modified current-mode vertical-cavity surface-emitting laser (VCSEL) driver as a transmitter for short-range light detection and ranging (LiDAR) sensors, where a stable bias generator is suggested with a regulated cascode current mirror circuit to provide the bias current of 1 mA with a trivial deviation of 5.4%, even at the worst-case process–voltage–temperature (PVT) variations. Also, a modified current-steering logic circuit is exploited with N-type MOSFET (NMOS) switches to deliver the modulation currents of 0.1~10 mApp to the VCSEL diode simultaneously, with no overshoot distortions. Post-layout simulations of the modified current-mode VCSEL driver (m-CMVD), using 180 nm CMOS technology, demonstrate very large and clean output pulses with significantly reduced signal distortions. Hereby, the VCSEL diode is transformed into an equivalent circuit with a 1.6 V DC voltage and a 50 Ω resistor for circuit simulations. The proposed m-CMVD consumes a maximum of 11 mW from a 3.3 V supply voltage and the chip core occupies an area of 0.196 mm2.

A Monostable Physically Unclonable Function Based on Improved RCCMs with 0–1.56% Native Bit Instability at 0.6–1.2 V and 0–75 °C

In this work, a Physically Unclonable Function (PUF) based on an improved regulated cascode current mirror (IRCCM) is presented. The proposed IRCCM improves the loop-gain of the gain-boosting branch over the conventional RCCM PUF, thereby increasing the output resistance and amplifying the mismatches due to random variations. The introduction of an explicit reference current in the biasing branch of the IRCCM results in lower native unstable bits, good robustness against environmental variations and very stable power consumption. The proposed PUF has been validated through measurement results on a test-chip implemented in a 130 nm CMOS process. The PUF performance was measured for supply voltages between 0.6 and 1.2V, and temperatures ranging from 0 °C to 75 °C. A comparison against similar designs from the literature has shown that the proposed PUF exhibits state of the art performance with improved reliability under supply voltage variations.

Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm

This paper presents a physically unclonable function (PUF) that can be designed with an automated digital design flow with a standard-cell approach. Compared to conventional PUFs designed in an analog or array style, the proposed PUF can be immersed in logic for inherent PUF obfuscation, and entails significantly lower design effort. The proposed PUF, belongs to the static monostable PUF class, is based on regulated cascode current mirrors (RCCM) and has hysteretic behavior to improve robustness against bit flips caused by noise, voltage, and temperature fluctuations. Hysteresis is achieved by inserting a Muller C-element in the PUF output stage and skewed inverters. The impact of temperature fluctuations on the stability is further reduced through a temperature compensation feedback loop. A 40-nm testchip was designed through a digital design flow based on the proposed PUF standard cell. Testchip measurements show native worst case bit error rate (BER) of 3.2% at 0.8–1.0-V voltage and 25 °C–85 °C temperature. A temperature sensitivity of 0.015%/°C in terms of PUF instability, an energy per bitcell of 1.02 fJ/b, and an autocorrelation function (ACF) of 0.00735 at 95% confidence are achieved, being the lowest reported to date. In view of the low design effort and low power consumption, the proposed PUF is amenable for low-cost and low-power systems on chip (SoC) (e. g., for Internet of Things applications).

Chopper-Stabilized Bidirectional Current Acquisition Circuits for Electrochemical Amperometric Biosensors

Two low-noise bidirectional current acquisition circuits for interfacing with electrochemical amperometric biosensor arrays are presented. The first design is a switched-capacitor transimpedance amplifier (TIA). The second design is a current conveyer (CC) with regulated-cascode current mirrors. Both circuits employ chopper stabilization to reduce flicker noise. The TIA and the CC were prototyped in 0.13 μm CMOS and consume 3 μW and 4 μW from a 1.2 V supply, respectively. The electrical and electrochemical recording properties of both circuits have been characterized. The current conveyer exhibits superior performance in low-concentration electrochemical catalytic reporter sensing, as less switching noise is injected into the biosensor.

FGMOS Based Low-Voltage Low-Power High Output Impedance Regulated Cascode Current Mirror

FGMOS Based Low-Voltage Low-Power High Output Impedance Regulated Cascode Current Mirror

Current mode read-out circuit for InGaAs photodiode applications

Infrared focal plane arrays have many military, industrial, medical, and scientific applications that require high-resolution and high-performance read-out electronics. In applications involving InGaAs sensor arrays, data read-out can be carried out by circuits implemented with 0.35μm CMOS technology. In this paper we propose a dynamically regulated cascode current mirror for pixel read-out. From simulation results, we expect this circuit to achieve a better trade-off between silicon area, signal-to-noise ratio, and output dynamic range than the trade-off that is currently achieved by current mode CMOS read-out circuits.

An improved regulated cascode current mirror

Current mirrors are frequently used in analog and mixed signal circuit design and because they appear so simple, their importance is sometimes overlooked. This work reports the design of an improved regulated cascode current mirror that offers very higher resolution (up to 15 bits) and high speed (up to 400 MHz). The performance of the circuit was analyzed using simulations based on a 0.8 μm biCMOS technology.

Current Mode Circuit Implementations of PWL Functions

Current-mode techniques have been used to realize improved basic building blocks of elementary piecewise linear (PWL) functions. These alternative circuit implementations, used for synthesis of precision PWL transfer characteristics, are described and compared in performance. In this paper, two optional topologies of the PWL function building blocks are proposed, based on the regulated cascode current mirror, current sources, Schottky “prebiased” diodes, and improved CMOS class AB “prebiased diodes.” The comparison of DC and high frequency performances is based on HSPICE simulation results and shows very good DC accuracy and transient time response of the proposed building blocks.