Refractory Metal Gate Research Articles

500 °C operation of β-Ga2O3 field-effect transistors

We demonstrated 500 °C operation of field-effect transistors made using ultra-wide bandgap semiconductor β-Ga2O3. Metal–semiconductor field-effect transistors were fabricated using epitaxial conductive films grown on an insulating β-Ga2O3 substrate, TiW refractory metal gates, and Si-implanted source/drain contacts. Devices were characterized in DC mode at different temperatures up to 500 °C in vacuum. These variable-temperature measurements showed a reduction in gate modulation of the drain current due to an increase in gate leakage across the gate/semiconductor Schottky barrier. Devices exhibited a reduction in transconductance with increasing temperature; despite this, drain current increased with temperature due to a reduction in threshold voltage caused by the de-trapping of electrons from deep-level traps. Devices also showed negligible change in semiconductor epitaxy and source/drain contacts, hence demonstrated recovery to their room-temperature electrical properties after the devices were tested intermittently at different high temperatures in vacuum. The mechanism of gate leakage was also explored, which implicated the presence of different conduction mechanisms at different temperatures and gate electric fields.

Thin channel β-Ga2O3 MOSFETs with self-aligned refractory metal gates

We report the first demonstration of self-aligned gate (SAG) β-Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs) as a path toward eliminating source access resistance for low-loss power applications. The SAG process is implemented with a subtractively defined and etched refractory metal, such as Tungsten, combined with ion-implantation. We report experimental and modeled DC performance of a representative SAG device that achieved a maximum transconductance of 35 mS mm−1 and an on-resistance of ∼30 Ω mm with a 2.5 μm gate length. These results highlight the advantage of implant technology for SAG β-Ga2O3 MOSFETs enabling future power switching and RF devices with low parasitic resistance.

Investigation of Mg Diffusion in Ta(N) Based Electrodes on HfO2 for Sub-32nm CMOS Gate-Last Transistors

Magnesium alloyed with Ta and TaN is investigated as possible gate electrode on HfO2 dielectric. When Mg is deposited on Ta, we observe TaMg alloy formation and HfO2 degradation induced by Mg annealed at 440{degree sign}C. When TaN is deposited on HfO2 prior to Mg, TaN acts as chemical barrier against Mg diffusion and minimizes direct reaction of Mg with HfO2. TaN controls the Mg diffusion through complex mechanisms. Beside, sub-stoichiometric TaNx electrode without any additive is stable on HfO2 at 440{degree sign}C, with N+ 4.3eV band-edge work-function. We discuss on the relevance to use low-work-function additive in refractory metal gate on HfO2 dielectric.

Reliability study on InAlAs/InGaAs HEMTs with an InP recess-etch stopper and refractory gate metal

Preliminary BT-stress tests for 0.1 μm-gate InAlAs/InGaAs HEMTs, with an InP recess-etch stopper and a refractory metal gate, were carried out. By employing WSiN as a gate metal, threshold voltage shift, caused by metal sinking into the InP recess-etch stopper during the fabrication process or thermal stresses after the gate formation, was eliminated. A decrease in saturation current is the major failure mode, where the activation energy in the 175–215°C temperature region and the extrapolated median lifetime at 125°C were estimated to be 1.6 eV and over 10 5 h, respectively. The observed failure mode is associated with an increase in drain resistance and is suggesting that the degradation mechanism is related to the applied field.

Self-Passivated Copper Gates For Thin Film Silicon Transistors

AbstractA solution to the thin film silicon transistor gate metallization problem in active matrix liquid crystal displays is demonstrated in the form of a self-passivation process for copper. Bottom-level copper (Cu) lines are passivated by a self-aligned CrOx encapsulation formed by surface segregation of chromium (Cr) from dilute Cu1-xCrx alloys (x=0.1–2.3) at 400°C. The encapsulation is an efficient barrier for Cu diffusion into the SiNx gate insulator during the plasma deposition and transistor processing, and solves the problems of oxidation and adhesion to the glass substrate. Gate line resistivities are 4.5 to 7.5μΩcm depending on the initial Cr concentration. The performance of self-passivated Cu-gate thin film transistors is comparable to that of transistors with refractory metal gates.

An all implanted self-aligned enhancement mode n-JFET with Zn gates for GaAs digital applications

An all implanted self-aligned n-channel JFET fabrication process is described where Zn implantation is used to form the p/sup +/ gate region. A refractory metal (W) gate contact is used to allow subsequent high temperature activation of the self-aligned Si source and drain implant. 0.7 /spl mu/m JFET's have a maximum transconductance of 170 mS/mm with a saturation current of 100 mA/mm at a gate bias of 0.9 V. The p/sup +//n homojunction gate has a turn on voltage of 0.95 V at a current of 1 mA/mm. The drain-source breakdown voltage is 6.5 V. Microwave measurements made at a gate bias of 1 V show an f/sub t/ of 19 GHz with an f/sub max/ of 36 GHz. These devices show promise for incorporation in both DCFL and complementary logic circuits. >

An all-implanted, self-aligned, GaAs JFET with a nonalloyed W/p/sup +/-GaAs ohmic gate contact

We describe a self-aligned, refractory metal gate contact, enhancement mode, GaAs junction field effect transistor (JFET) where all impurity doping was done by ion implantation. Processing conditions are presented for realizing a high gate turn-on voltage (/spl sim/1.0 V at 1 mA/mm of gate current) relative to GaAs MESFET's. The high gate turn-on voltage is the result of optimizing the p/sup +/-gate implant and anneal to achieve a nonalloyed ohmic contact between the implanted p/sup +/-GaAs and the sputter deposited tungsten gate contact. Initial nominally 1.0 /spl mu/m/spl times/50 /spl mu/m n-JFET's have a transconductance of 85 mS/mm and f/sub t/ of 11.4 GHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Effects of neutral buried p-layer on high-frequency performance of GaAs MESFETs

Fully ion-implanted n/sup +/ self-aligned GaAs MESFETs with Au/WSiN refractory metal gates have been fabricated by adopting neutral buried p-layers formed by 50-keV Be-implantation. S-parameter measurements and equivalent circuit fittings are discussed. When the Be dose is increased from 2*10/sup 12/ cm/sup -2/ to 4*10/sup 12/ cm/sup -2/, the maximum value of the cutoff frequency with a 0.2- mu m gate falls off from 108 to 78 GHz. This is because a neutral buried player makes the intrinsic gate-source capacitance increase markedly, while its influence on gate-drain capacitance and gate-source fringing capacitance is negligible. The maximum oscillation frequency recovers, however, due primarily to the drain conductance suppression by the higher-concentration buried p-layer. An equivalent value of over 130 GHz has been obtained for both 0.2- mu m-gate GaAs MESFETs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Laser Processed Silicides for GaAs Hemts

ABSTRACTLaser annealed refractory metal gates and Ohmic contacts have been developed for GaAs FETs and HEMTs fabricated on MBE layers grown on laser desorbed substrates. Amorphous refractory metal silicide films were sputter deposited by a method in which the RF power to separate refractory metal and silicon targets were set at predetermined deposition ratesand the substrates were rotated with respect to the sputter targets receiving a 0.2 to 0.5 nm film on each pass. The gate resistance was reduced and Ohmic contacts formed by pulsed excimer laser annealing.

A 630-mS/mm GaAs MESFET with Au/WSiN refractory metal gate

GaAs MESFET's with a gate length as low as 0.2 mu m have been successfully fabricated with Au/WSiN refractory metal gate n/sup +/-self-aligned ion-implantation technology. A very thin channel layer with high carrier concentration was realized with 10-keV ion implantation of Si and rapid thermal annealing. Low-energy implantation of the n/sup +/-contact regions was examined to reduce substrate leakage current. The 0.2- mu m gate-length devices exhibited a maximum transconductance of 630 mS/mm and an intrinsic transconductance of 920 mS/mm at a threshold voltage of -0.14 V.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Comparison of low temperature and high temperature refractory metal/silicides self-aligned gate on GaAs

Since the first reported use of TiW gate as a stopping mask for n+ implantation for GaAs self-aligned gate field effect transistors (SAGFET) in 1981, refractory metal compounds and silicides have found a widespread use in the GaAs SAGFET technology. However, the technique requires that the refractory metal (silicide)/GaAs interface be subjected to a high temperature postimplantation annealing, typically 750–900 °C. The mechanical, metallurgical, and most sensitively the electrical stabilities and reproducibility of the refractory metal (silicide)/GaAs Schottky barrier characteristics have become the major issues confronting the high temperature SAGFET technology. The use of a dielectric substitutional gate, which allows the refractory metal gate to be formed at a low temperature, typically room temperature to 400 °C, for fabrication of SAGFET was reported in 1983. With the advance of well controlled dry etching and photoresist planarization techniques, the low temperature SAGFET process becomes a potentially viable alternate technology. In this paper, comparisons of the two technologies and associated device performances are made. The basic issues of refractory metal/GaAs and dielectric/GaAs interface reactions, stress and impurity incorporation at high annealing temperatures are discussed.

Fabrication of Highly Reliable Tungsten Gate MOS VLSI's

Recently, refractory metals, such as W and Mo, with low resistivity and a high melting point have received keen interest as materials for gate electrodes and interconnects for MOS VLSI's. However, it is commonly believed that MOS devices with refractory metal gates have low reliability due to mobile ion contamination. In this work, it was clarified that W gates with commercially available W sputtering targets introduced high level mobile charges into the gate oxide. It was also found that the rates of degradation of W gate MOS transistors due to hot carriers were higher than those of poly‐Si gates, and the internal stresses in W gates increased the degradation rates. Therefore, the authors developed a high purity W sputtering target fabrication technique through the use of electron melting. A W gate annealing technique was developed to reduce the internal stress in W films. Through these techniques, the above‐mentioned problems can be eliminated, and W gate devices that have characteristics comparable to those of poly‐Si gates can be produced.

Submicrometer FET gate fabrication using resistless and focused ion beam techniques

We report using a focused ion beam lithography, without the use of organic resists, to produce submicrometer gates. Refractory metal gates of WTi, with a minimum length near 0.1 μm, and p-type polysilicon gates, with lengths down to 0.5 μm, were fabricated. The gate lithography utilizes focused beams of Si++ or B+ ions produced from Au–Si or B–Pt alloy liquid metal ion sources and a three-lens mass-separating focusing column. We found that using proper implant and subsequent etch conditions causes the gate material to behave as a negative resist thus enabling gate definition. NMOS FET’s were fabricated with the WTi and p-type Si gates using these techniques and these devices had gate oxide thicknesses of 38 and ∼13 nm. The gate lengths varied between 2.0 and 0.15 μm. Transconductances as large as 180 mS/mm were obtained.

A new tungsten gate process for VLSI applications

In spite of the growing demand for MOS gates and interconnections of higher conductivity, the refractory metal gate process has not received as much attention as those using silicides because it is incompatible with the Si-gate process. The metal gate cannot withstand oxidizing annealing ambients, and source-drain formation by ion implantation is difficult because of the channeling of doping ions through the gate metal during ion implantation. In a new process developed for use in MOS VLSI fabrication, tungsten (W) is used as a gate metal because degradation of SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> by annealing the metal/SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> /Si structure at around 1000°C can be minimized if the metal is W. Metal oxidation is prevented by using a H <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> /H <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> O ambient for this annealing, which also allows Si to be oxidized in the same ambient. The channeling mentioned above is stopped by forming a thin layer of PSG or WO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> on the W. This gate process is believed to be a step forward toward the desired compatibility.

Refractory metal gate processes for VLSI applications

The conventional n-channel silicon-gate MOS technology faces limitations due to poly-sheet resistance, patterning, and overall process compatibility as feature dimensions shrink and circuit sizes increase. This work describes an investigation of refractory metals as alternate gate material due to their potential advantages in terms of patternability, film sheet resistance that is 50 to 100 times lower comparable to polysilicon, and circuit layout options with improved performance and cost effectiveness. A process was developed for fabrication of NMOS devices using electron-beam direct writing, refractory metal gates and interconnects. Evaporated as well as sputtered molybdenum and tungsten show columnar crystalline structure allowing reproducible patterning of 1-µm lines with the conventional plasma etch techniques. Sheet resistivities of 0.25 Ω/□ and 0.4 Ω/□ were achieved for 3500-Å Mo and W films, respectively. Basic parameters such as electronic work function, interface, and surface state charge densities and MOS transistor threshold voltages were determined from metal gate devices with 200-800-Å oxides. Flat-band voltages of -0.2 V with mid 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> interface charges were achieved. Mo-Al-Si double-level metal structure with contacts as small as 2 µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> were fabricated. Considerable improvement in the speed of the LSI circuits fabricated with these high-conductivity gates was demonstrated through computer simulation. Improved circuit layouts of static and dynamic memory cells for speed, power, and density optimization can be achieved. A four-mask process with the simplicity of aluminum gate technology and the performance of current n-channel silicon gate MOS process is proposed.

Fabrication of short channel MOSFETs with refractory metal gates using RF sputter etching

Fabrication of sub-μm p-channel MOSFETs with refractory metal gates using novel refinements of conventional photolithographic procedures is described. The method avoids the need for direct electron beam writing on the wafer and for ion implantation instead of diffusion. Autoregistration Mo gate structures down to 2 μm corresponding to an estimated channel length of 0 · 7 μm were made using RF sputter etching for the drain-source windows while masking with a positive photoresist. This was contact patterned using a chromium-on-glass mask made by electron beam writing and RF sputter etching. Sputter-deposited boron-doped SiO 2 was used as the diffusion source for the source-drain areas. The transistors were made on (100) phosphorus doped n-type silicon with an impurity concentration of 2 . 10 16 cm −3. Fabricated devices with channel lengths ≥ 1 · 7 μm had an apparent threshold voltage of 2·5 V (10 μA criterion) and for 1·7 μm channel length an apparent punch-through voltage of 18 V. A sputtered Mo layer ⋍ 1 μm thick was used as gate material. A distinct advantage of using sputter etching with a single system capable of both deposition and etching is that it is possible to go directly to the next steps without exposure to air. These steps are mask removal in a partial H 2 and O 2 plasma, followed by further Argon sputter-etching and sputter deposition of a doped oxide diffusion source on the sputter-etched cleaned surface. This promises a better reproducibility of surface doping as there should be less oxide and less contamination than in conventional processes. The characteristics of the fabricated transistors did not indicate any un-annealable drift or gate oxide damage due to the presence of the plasma provided the Mo layer was sufficiently thick. Thus sputter etching which offers good resolution can be used in MOS fabrication. Due to its lower resistivity, Mo, which can be used an an additional interconnection layer (isolated from the A1 layer) offers better speed potential than Si, in certain types of circuits, e.g. high speed memories with long address lines. With a proper background doping of the wafer and diffusion time and temperature it was possible to obtain ⋍ 0 · 6 μm lateral diffusion below the gate from both source and drain regions. It was thus possible to obtain sub-μm p-channel MOSFETs even while working close to the limits of normal optical contact production of micropatterns, which is 1–2 μm.

Fabrication of short channel MOSFETS with refractory metal gates using RF sputter etching : A. Rodriguez, M. Misra, H. Hesselbom and P. A. Tove. Solid State Electronics19. 17 (1976)

Fabrication of short channel MOSFETS with refractory metal gates using RF sputter etching : A. Rodriguez, M. Misra, H. Hesselbom and P. A. Tove. Solid State Electronics19. 17 (1976)

Performance of refractory metal multilevel interconnection system

High-temperature multilevel interconnection systems are discussed from a materials fabrication, yield, and circuit performance point of view. Refractory metal interconnections are compared to diffused Si planar runs and heavily doped polycrystalline Si films. Circuit configurations and their relative importance for these material-circuit performance considerations are considered. All of the high-temperature refractory systems will have higher yield and better passivation properties than many low-temperature systems. Metallic interconnections are always best from a circuit performance point of view. The relative difference between the high-temperature systems considered depends on circuit configuration. In particular, high-temperature refractory metal (Mo, W) interconnections which are a natural by-product of the self-registered refractory metal gate MOS technology (RMOS) are superior for memory circuits where long address lines are used.

Refractory metal silicon device technology

Films 2000–5000 Å thick of Mo or W deposited over thin films of thermally grown SiO 2 are shown to be effective high temperature diffusion masks against both phosphorous and boron. These metal films may be precisely patterned and their diffusion masking properties can be used to define the source and drain regions of MOSFETs. In this manner, self-registered MOSFETs can be fabricated with a portion of the diffusion masking metal film acting as the gate electrode. Using P or B doped deposited glasses as diffusion sources, n or p channel enhancement mode MOSFETs were made by diffusion through the exposed thin SiO 2 film into p and n type Si to form source and drain junctions. Contact was subsequently made by etching holes through the oxide layers to the source and drain regions and to the refractory metal gate electrode buried within the oxide layers. These devices exhibit channel mobilities between 200 and 300 cm 2/V-sec at gate voltages about 10 V above threshold. The stability of MOS structures processed in a similar manner has been measured. After being stressed at ±6 × 10 5 V/ cm and 250°C for 15 hr, these devices exhibited shifts in their CV characteristics less than 200 mV.