Reference Clock Generator Research Articles

Investigation of injection‐locked ring oscillators for process, voltage, and temperature‐aware low phase‐noise reference clock generation

In this paper, injection-locked coupled ring oscillators (ROs) are studied regarding their capabilities for process, voltage, and temperature (PVT) compensated reference clock generation. A PVT resilient RO is implemented by means of injection-locked coupled ROs where the injection locking mechanism is realized by employing adjustable coupling factors. It is shown that the oscillation frequency can be highly compensated for temperature-related variations through the coupling factors. In addition, it is possible to compensate the center oscillation frequency for process-induced variations and supply voltage fluctuations. The proposed technique is fully open loop without any frequency tracking loop and can be easily adopted by other architectures of oscillators such as RC and LC counterparts. A 2.4 GHz reference clock generator is implemented in a 0.18 μm standard CMOS process. While the temperature coefficient (TC) of the free-running ROs is about 640 ppm/°C, the coupled structure offers a TC of 80 ppm/°C. Furthermore, the phase-noise of the coupled structure is about 4 dB lower compared with the free-running ROs. The proposed RO consumes about 2.8 mW and occupies a silicon area of 0.09 mm2.

Drone-Based External Calibration of a Fully Synchronized Ku-Band Heterodyne FMCW Radar

This paper discusses a novel drone-based external radar calibration technique, which utilizes a metal sphere hanging from a drone. The advantages of drone-based calibration are introduced and applied to a dual intermediate-frequency frequency-modulation continuous-wave (FMCW) radar system, which was developed to detect a low radar cross section (RCS) target like a drone with high sensitivity. The developed radar system operates in 150-MHz bandwidth with a frequency sweeping time of $500~\mu \text{m}$ at Ku-band frequencies. A 75- $\Omega $ coaxial cable was utilized in the radar system to physically separate the transmitter (Tx) and receiver (Rx) modules for better isolation. The physical separation with a coaxial cable helps in reducing Tx leakage signal effect, which is a critical concern of typical FMCW radar system, and also it helps the proposed radar system to have higher sensitivity. The designed radar system is a wired system that is fully synchronized with an internal reference clock generator. Offset frequency and other compensation factors were calculated for the calibration of the radar system using a big size metal sphere hanging from a drone. We observed that the theoretical calculations using the standard radar equation and the measurement results on calibration are in good agreement with each other. Furthermore, the RCS value of a small size drone is also investigated using the calibrated radar system. The RCS value estimated for the drone was about −22 dBsm.

Wide-range CMOS reference clock generator with a dynamic duty cycle scaling mechanism at a 0.9-V supply voltage

This paper presents a wide-range CMOS reference clock generator with a dynamic duty cycle scaling mechanism. A new duty-cycle-to-voltage converter (DCVC) is proposed for the clock generator, which requires only the duty cycles of differential 25-MHz input signals. When these duty cycles are set into the DCVC, dual control voltages, namely VP and VN with positive and negative control duty cycle coefficients, respectively, are produced to manage the current sources of the differential voltage-controlled ring oscillator and supply a wide range of frequency channels. The proposed clock generator can supply a stable output clock with a wide range of frequencies from 37 kHz to 34 MHz. Notably, the wide-range CMOS reference clock generator can also be used in a universal serial bus hub or in wide band applications with low supply voltages and small areas.

Development of low‐complexity all‐digital frequency locked loop as 500 MHz reference clock generator for field‐programmable gate array

The authors report the development of an on-chip 500 MHz reference clock generator as a part of a clock manager for a field-programmable gate array. The generator is implemented in the form of an all-digital frequency locked loop (ADFLL) in architecture of low complexity and high modularity. For the development of the ADFLL, they propose a new circuit that employs two under-sampled 1-bit ΔΣ frequency-to-digital converters to convert a frequency difference into a proportional distributed pulsewidth. By the combination of the proposed circuit with a conventional phase-and-frequency detector, a frequency comparator is implemented and can indicate its two input frequency conditions, that is, (i) equal to, (ii) lower than or (iii) higher than. The ADFLL which adopts the proposed frequency comparator is implemented in a 90 nm CMOS technology. Consuming 2.64 mW from a 1.2 V supply, the ADFLL shows about 50 µs of locking time at the frequency accuracy of 99.2% while operating at 500 MHz and being driven by a 10 MHz reference clock.

Analysis of a Frequency Acquisition Technique With a Stochastic Reference Clock Generator

This brief presents a theoretical analysis of the stochastic reference clock generator (SRCG), which creates a clock like periodic signal from a random nonreturn-to-zero data sequence. The output of the SRCG can be utilized as a reference clock for frequency acquisition in dual-loop clock-and-data recovery circuits. A frequency-locked loop (FLL) subsequent to the SRCG guides the voltage-controlled oscillator frequency into the pull-in range of the phase-locked loop while suppressing the high-frequency phase noise of the SRCG. The phase noise and frequency offset of the SRCG-FLL pair are analyzed. The validity of the theoretical analysis is supported by results taken from a test chip.