Reed-Muller Expansions Research Articles

Enhancing the quantum cost of Reed-Muller Based Boolean quantum circuits using genetic algorithms

There is a direct equivalence between Boolean functions represented in Reed-Muller logic and Boolean Quantum Circuits. Different polarity Reed-Muller expansions will give different Boolean quantum circuits with different cost for the same Boolean function. For a given Boolean function with n variables there are 2n possible expansions. Searching for the expansion that gives a Boolean quantum circuit with minimum quantum cost within the search space is a hard problem for large n. This paper will use genetic algorithms to find the fixed/mixed polarity Reed-Muller expansion that gives a Boolean quantum circuit with minimum quantum cost to optimize the circuit realization of a given Boolean function.

Improving the quantum cost of reversible Boolean functions using reorder algorithm

This paper introduces a novel algorithm to synthesize a low-cost reversible circuits for any Boolean function with n inputs represented as a Positive Polarity Reed–Muller expansion. The proposed algorithm applies a predefined rules to reorder the terms in the function to minimize the multi-calculation of common parts of the Boolean function to decrease the quantum cost of the reversible circuit. The paper achieves a decrease in the quantum cost and/or the circuit length, on average, when compared with relevant work in the literature.

Function Synthesis Algorithm of RTD-Based Universal Threshold Logic Gate

The resonant tunneling device (RTD) has attracted much attention because of its unique negative differential resistance characteristic and its functional versatility and is more suitable for implementing the threshold logic gate. The universal logic gate has become an important unit circuit of digital circuit design because of its powerful logic function, while the threshold logic gate is a suitable unit to design the universal logic gate, but the function synthesis algorithm for then-variable logical function implemented by the RTD-based universal logic gate (UTLG) is relatively deficient. In this paper, three-variable threshold functions are divided into four categories; based on the Reed-Muller expansion, two categories of these are analyzed, and a new decomposition algorithm of the three-variable nonthreshold functions is proposed. The proposed algorithm is simple and the decomposition results can be obtained by looking up the decomposition table. Then, based on the Reed-Muller algebraic system, the arbitraryn-variable function can be decomposed into three-variable functions, and a function synthesis algorithm for then-variable logical function implemented by UTLG and XOR2 is proposed, which is a simple programmable implementation.

모서리값 확장 그래프를 사용한 함수구성에 관한연구

In recently years, many digital logic systems based on graph theory are analyzed and synthesized. This paper presented a method of constructing the function using edge valued extension graph which is based on graph theory. The graph is applied to a new data structure. from binary graph which is recently used in constructing the digital logic systems based on the graph theory. We discuss the mathematical background of literal and reed-muller expansion, and we discuss the edge valued extension graph which is the key of this paper. Also, we propose the algorithms which is the function derivation based on the proposed edge valued extension graph. That is the function minimization method of the n-variables m-valued functions and showed that the algorithm had the regularity with module by which the same blocks were made concerning about the schematic property of the proposed algorithm.

Mixed Radix Reed-Muller Expansions

The choice of radix is crucial for multivalued logic synthesis. Practical examples, however, reveal that it is not always possible to find the optimal radix when taking into consideration actual physical parameters of multivalued operations. In other words, each radix has its advantages and disadvantages. Our proposal is to synthesize logic in different radices, so it may benefit from their combination. The theory presented in this paper is based on Reed-Muller expansions over Galois field arithmetic. The work aims to first estimate the potential of the new approach and to second analyze its impact on circuit parameters down to the level of physical gates. The presented theory has been applied to real-life examples focusing on cryptographic circuits where Galois Fields find frequent application. The benchmark results show that the approach creates a new dimension for the trade-off between circuit parameters and provides information on how the implemented functions are related to different radices.

Perfect Shuffle에 의한 5치 논리회로의 구성에 관한 연구

본 논문에서는 Perfect Shuffle에 의한 5치 논리 회로의 구성에 관한 한 가지 방법을 제시하였다. 먼저, Perfect Shuffle 기법과 Kronecker 곱에 의한 5치 논리함수의 입출력 상호연결에 대하여 논하였고, GF(5)의 가산회로와 승산회로를 이용하여 5치 Reed-Muller 전개식의 변환행렬과 역변환행렬을 실행하는 기본 셀을 설계하였다. 이 기본 셀들과 Perfect Shuffle과 Kronecker 곱에 의한 입출력 상호연결 방법을 이용하여 5치 Reed-Muller 전개식에 의한 5치 논리 회로를 구현하였다. 제시된 5치 Reed-Muller 전개식의 설계방법은 모듈구조를 기반으로 하여 행렬변환을 이용하므로 동일한 함수에 대하여 타 방법과 비교하여 간단하고 회로의 가산회로와 승산회로를 줄이는데 매우 효과적이다. 제안된 5치 논리회로의 설계방법은 회선경로 선택의 규칙성, 간단성, 배열의 모듈성과 병렬동작의 특징을 가진다. In this paper, we present a method on the construction of quinternary logic circuits using Perfect shuffle. First, we discussed the input-output interconnection of quinternary logic function using Perfect Shuffle techniques and Kronecker product, and designed the basic cells of performing the transform matrix and the reverse transform matrix of quinternary Reed-Muller expansions(QRME) using addition circuit and multiplication circuit of GF(5). Using these basic cells and the input-output interconnection technique based on Perfect Shuffle and Kronecker product, we implemented the quinternary logic circuit based on QRME. The proposed design method of QRME is simple and very efficient to reduce addition circuits and multiplication circuits as compared with other methods for same logic function because of using matrix transform based on modular structures. The proposed design method of quinternary logic circuits is simple and regular for wire routing and possess the properties of concurrency and modularity of array.

A Fast Algorithm for Synthesis of Quantum Reversible Logic Circuits

Reversible logic finds many applications,especially in the area of quantum computing. Quantum reversible logic circuits are basic elements in quantum computer construction. Synthesis of quantum reversible logic circuits means to automatically construct desired quantum reversible logic circuit with minimal quantum cost. The authors absorb different ideas of reversible logic circuits synthesis and present a novel and efficient algorithm which can automatically derive the positive polarity Reed-Muller expansion (RM). A solution space tree is constructed to create quantum reversible logic circuits. Firstly,floor traversal is applied globally,and depth-first search is used locally. Secondly,according to the technique of template optimization,the bound function is constructed,which can rapidly prune the branches with no or nonoptimal result. Thirdly,factors of RM are first considered,therefore the algorithm can effectively construct optimal result and saves computational cost significantly. Judging by the internationally recognized reversible functions of three variables,the proposed algorithm not only synthesizes all optimal reversible functions,but also runs extremely faster than others of the same kind.

Reed-Muller 전개식에 의한 다치 논리회로의 구성에 관한 연구

In this paper, we present a method on the construction of multiple-valued circuits using Reed-Muller Expansions(RME). First, we discussed the input output interconnection of multiple valued function using Perfect Shuffle techniques and Kronecker product and designed the basic cells of performing the transform matrix and the reverse transform matrix of multiple valued RME using addition circuit and multiplication circuit of GF(4). Using these basic cells and the input-output interconnection technique based on Perfect Shuffle and Kronecker product, we implemented the multiple valued logic circuit based on RME. The proposed design method of multiple valued RME is simple and very efficient to reduce addition circuits and multiplication circuits as compared with other methods for same function because of using matrix transform based on modular structures. The proposed design method of multiple valued logic circuits is simple and regular for wire routing and possess the properties of concurrency and modularity of array.

Techniques for dual forms of Reed–Muller expansion conversion

Dual Forms of Reed–Muller (DFRM) are implemented in OR/XNOR forms, which are based on the features of coincidence operation. Map folding and transformation techniques are proposed for the conversion between Boolean and DFRM expansions. However, map techniques can only be used for up to 6 variables. To overcome the limitation, serial tabular technique (STT) and parallel tabular technique (PTT) are proposed. STT deals with one variable at a time while PTT generates terms in parallel. Both tabular techniques outperform significantly published work in terms of conversion time. Methods based on on-set canonical sum-of-products minterms and canonical product-of-sums maxterms are also investigated.

An Algorithm for Synthesis of Reversible Logic Circuits

Reversible logic finds many applications, especially in the area of quantum computing. A completely specified n-input, n-output Boolean function is called reversible if it maps each input assignment to a unique output assignment and vice versa. Logic synthesis for reversible functions differs substantially from traditional logic synthesis and is currently an active area of research. The authors present an algorithm and tool for the synthesis of reversible functions. The algorithm uses the positive-polarity Reed-Muller expansion of a reversible function to synthesize the function as a network of Toffoli gates. At each stage, candidate factors, which represent subexpressions common between the Reed-Muller expansions of multiple outputs, are explored in the order of their attractiveness. The algorithm utilizes a priority-based search tree, and heuristics are used to rapidly prune the search space. The synthesis algorithm currently targets the generalized n-bit Toffoli gate library. However, other algorithms exist that can convert an n-bit Toffoli gate into a cascade of smaller Toffoli gates. Experimental results indicate that the authors' algorithm quickly synthesizes circuits when tested on the set of all reversible functions of three variables. Furthermore, it is able to quickly synthesize all four-variable and most five-variable reversible functions that were in the test suite. The authors also present results for some benchmark functions widely discussed in literature and some new benchmarks that the authors have developed. The algorithm is shown to synthesize many, but not all, randomly generated reversible functions of as many as 16 variables with a maximum gate count of 25

Quaternary Fixed-Polarity Reed–Muller expansion computation through operations on disjoint cubes and its comparison with other methods

A new algorithm for calculating quaternary Fixed-Polarity Reed–Muller (FPRM) spectra is described in this paper. The presented algorithm directly converts array of disjoint cubes representation of a quaternary function into its FPRM spectral coefficients. The main advantage of this algorithm is that it requires less memory space than other algorithms. Since each spectral coefficient can be calculated independently of other spectral coefficients, the algorithm can be implemented using parallel programming. Brief reviews and experimental results of several existing algorithms for the calculation of quaternary FPRM spectra are also included in this paper together with experimental results of the new algorithm for comparison purpose.

Representation of Boolean quantum circuits as reed–Muller expansions

In this paper we show that there is a direct correspondence between Boolean quantum operations and certain forms of classical (non-quantum) logic known as Reed–Muller expansions. This allows us to readily convert Boolean circuits into their quantum equivalents. A direct result of this is that the problem of synthesis and optimization of Boolean quantum circuits can be tackled within the field of Reed–Muller logic.

Walsh-Hadamard Optimization of Fixed Polarity Reed-Muller Transform

By investigating links between Reed-Muller transform and Walsh-Hadamard spectra an exact and non-exhaustive algorithm for the generation of optimal Reed-Muller expansions directly from just few Walsh-Hadamard spectral coefficients has been developed. The algorithm makes use of the properties of Walsh-Hadamard spectra and by using only few Walsh-Hadamard coefficients the optimal Reed-Muller expansion is obtained for all Boolean functions through the provided equations in the new algorithm.

Simplified Reed?Muller Expressions for Residue Threshold Functions

Residue threshold functions are a broad class of Boolean functions which includes all the unit-weighted threshold functions. In this paper we investigate the complexity of the Reed-Muller (RM) expressions for these functions. We prove that an important subclass of them has very simple RM expansions and determines the conditions that define it. As an interesting practical application, we show that the output functions of parallel counters belong to this subclass.

A new approach to generate fixed-polarity Reed–Muller expansions for completely and incompletely specified functions

Generally, the application of Exclusive-OR (ExOR) logic design suffers from a lackof straightforward methods. In this paper, based on the Boolean matrixrepresentation, the author introduces a new approach associated with a fast,simple, straightforward and computationally effective algorithm to obtain theminimum Reed–Muller ExOR expansion with fixed polarity. The new algorithmcan be applied to completely as well as incompletely specified functions and itapplies no constraints on the number of variables within any given switchingfunction. The proposed minimization approach is based on the Boolean matrixrepresentation and minterm separation operation to generate a fixed polarityReed–Muller expansion that has a minimum number of non-zero valued terms inthe final expansion while having a minimum numberof total literals. This is doneefficiently and directly without involving exhaustive search procedures. For the caseof an incompletely specified function, the algorithm tries to deduce the bestselection of the ‘Don’t care’ term values while searching for a minimal fixedpolarity Reed–Muller expansion. Demonstration examples with analysis resultsare illustrated and a comparison with other algorithms is introduced. In all theexamples from the literature, the solutions were either the same or better than thoseof other methods. In addition, the proposed algorithm enables rapid processing,efficiently treating the incompletely specified functions, with no logical constrainton the number of function variables. The significant advantages of the approachare its convenience for computer implementation and its ability to deal withproblems of very high dimension.

Perfect Shuffle에 의한 Reed-Muller 전개식에 관한 다치 논리회로의 설계

본 논문에서는 Perfect Shuffle 기법과 Kronecker 곱에 의한 다치 신호처리회로의 입출력 상호연결에 대하여 논하였고, 다치 신호처리회로의 입출력 상호연결 방법을 이용하여 유한체 GF<TEX>$(p^m)$</TEX>상에서 다치 신호처리가 용이한 다치 Reed-Muller 전개식의 회로설계 방법을 제시하였다. 제시된 다치 신호처리회로의 입출력 상호연결 방법은 모듈구조를 기반으로 하여 행렬변환을 이용하면 회로의 가산게이트와 승산게이트를 줄이는데 매우 효과적임을 보인다. GF<TEX>$(p^m)$</TEX>상에서 다치 Reed-Muller 전개식에 대한 다치 신호처리회로의 설계는 GF（3）상의 기본 게이트들을 이용하여 다치 Reed-Muller 전개식의 변환행렬과 역변환행렬을 실행하는 기본 셀을 설계하였고, 다치 신호처리회로의 입출력 상호연결 방법을 이용하여 기본 셀들을 상호연결하여 실현하였다. 제안된 다치 신호처리회로는 회선경로 선택의 규칙성, 간단성, 배열의 모듈성과 병렬동작의 특징을 가지므로 VLSI 화에 적합하다 In this paper, the input-output interconnection method of the multiple-valued signal processing circuit using Perfect Shuffle technique and Kronecker product is discussed. Using this method, the circuit design method of the multiple-valued Reed-Muller Expansions (MRME) which can process the multiple-valued signal easily on finite fields GF<TEX>$(p^m)$</TEX> is presented. The proposed input-output interconnection methods show that the matrix transform is an efficient and the structures are modular. The circuits of multiple-valued signal processing of MRME on GF<TEX>$(p^m)$</TEX> design the basic cells to implement the transform and inverse transform matrix of MRME by using two basic gates on GF(3) and interconnect these cells by the input-output interconnection technique of the multiple-valued signal processing circuits. The proposed multiple-valued signal processing circuits that are simple and regular for wire routing and possess the properties of concurrency and modularity are suitable for VLSI.

Efficient algorithm to calculate Reed–Muller expansions over GF(4)

A new algorithm to generate the full polarity matrix of fixed polarity Reed-Muller expansions over Galois fields of order 4, GF(4), has been developed. By using directly the truth vector of the original function, a recursive formula is developed to generate the whole polarity matrix. The algorithm uses the properties of the fixed polarity matrix to speed up the calculation and reduce the number of necessary multipliers and adders. The computational complexity of the algorithm is compared with other works. It is shown that, for practical hardware implementations of quaternary functions, the new algorithm is better than all other existing algorithms. The fast flow diagrams for computation of the whole or partial matrix are also presented.

Optimization of fixed-polarity Reed-Muller circuits using dual-polarity property

In the optimization of canonical Reed-Muller (RM) circuits, RM polynomials with different polarities are usually derived directly from Boolean expressions. Time efficiency is thus not fully achieved because the information in finding RM expansion of one polarity is not utilized by others. We show in this paper that two fixed-polarity RM expansions that have the same number of variables and whose polarities are dual can be derived from each other without resorting to Boolean expressions. By repeated operations, RM expansions of all polarities can be derived. We consequently apply the result in conjunction with a hypercube traversal strategy to optimize RM expansions (i.e., to find the best polarity RM expansion). A recursive route is found among all possible polarities to derive RM expansion one by one. Simulation results are given to show that our optimization process, which is simpler, can perform exhaustive search as efficiently as other good exhaustive-search methods in the field.

Comments on "Sympathy: fast exact minimization of fixed polarity Reed-Muller expansion for symmetric functions"

The above paper finds an optimal fixed-polarity Reed-Muller expansion of an n-variable totally symmetric function using an OFDD-based algorithm that requires O(n/sup 7/) time and O(n/sup 6/) storage space. However, an algorithm based on Suprun's transient triangles requires only O(n/sup 3/) time and O(n/sup 2/) storage space. An implementation of this algorithm yields computation times lower by several orders of magnitude.

Minimization of k-Variable-Mixed-Polarity Reed-Muller Expansions

A lookup table based method to minimize Generalized Partially-Mixed-Polarity Reed-Muller (GPMPRM) expansions with k mixed polarity variables has been developed. The new algorithm can produce solutions based on the desired cost criteria for the systems of completely specified functions.