Redundant Binary Signed-digit Research Articles

Improving Architectures of Binary Signed-Digit CORDIC With Generic/Specific Initial Angles

Coordinate rotation digital computer (CORDIC) is widely used in digital signal processing (DSP) to calculate functions. One of the elegant ways to accelerate CORDIC is employment of the redundant binary signed-digit (BSD) number systems, so-called BSD-CORDIC. This paper aims to achieve efficient BSD-CORDIC structures for generic/specific initial angles. First, three generic BSD-CORDIC algorithms are optimized by exploiting a suitable data gating technique as well as appropriate BSD encodings. The synthesis results demonstrate that for generic CORDIC, the proposed BSD-CORDIC schemes enhance the existing ones in terms of speed, power consumption, and area overhead. Second, the look-ahead BSD-CORDIC is proposed as a special case of BSD-CORDIC with specific initial angles. We also show that for the applications like fast Fourier transform (FFT), where the initial angles are known in advance, the proposed look-ahead BSD-CORDIC with the posibit-negabit encoding, as our best presenting structure, noticeably improves speed, power consumption, and area overhead.

Area–Time–Power Efficient FFT Architectures Based on Binary-Signed-Digit CORDIC

Fast Fourier transform (FFT) is a significant technique in the digital signal processing (DSP). The intrinsic weak point of the primary designs of FFT was the use of multipliers. CORDIC is the most prevalent method to replace the multipliers of FFTs. In order to enhance the speed of CORDIC, redundant binary signed-digit (BSD) encodings can be utilized, so-called BSD-CORDIC. The main goal of this paper is to improve the efficiency of BSD-CORDIC-based FFT. The redundant improved composed (RIC) CORDIC is proposed as a novel BSD-CORDIC. The main idea behind the RIC CORDIC lies in prior determination of the required iterations in such a way that the maximum number of iterations is reduced, which results in speedup and decrease in hardware resources. Also, some of the iterations still can be skipped, which leads to further reduction in the power consumption. The synthesis results demonstrate that the FFT based on the RIC BSD-CORDIC enhances speed, power consumption, and area overhead.

The Impact of Alternative Encoding Techniques on Field Programmable Gate Array Implementation of Sigma-Delta Modulated Ternary Finite Impulse Response Filters

This paper presents the design and synthesis of a single-bit ternary finite impulse response filter with balanced ternary coefficients (ie. -1, 0, +1) implemented in VHDL on small commercial field programmable gate arrays (FPGAs). A comparison is made between implementations based on 2s complement, redundant binary signed digit (RBSD) and canonical signed digit (CSD) encoding techniques. Through simulation, the area and performance of an example filter are analysed using pipelined and non-pipelined modes for all three techniques. The simulation results show that, unlike in the equivalent multi-bit filters, CSD offers no advantages in single-bit sigma-delta modulated (∑ΔM) systems. Similarly, RBSD occupies twice the area and exhibits much poorer performance compared to a conventional 2s complement representation due to the small symbol size in single-bit systems. These results demonstrate that simple, short word length ∑ΔM filters will be useful in greatly reducing the number of general-purpose digital multipliers in general purpose digital signal processor applications using FPGA and especially ASIC.

The impact of alternative encoding techniques on field programmable gate array implementation of sigma-delta modulated ternary finite impulse response filters

This paper presents the design and synthesis of a single-bit ternary finite impulse response filter with balanced ternary coefficients (ie. -1, 0, +1) implemented in VHDL on small commercial field programmable gate arrays (FPGAs). A comparison is made between implementations based on 2s complement, redundant binary signed digit (RBSD) and canonical signed digit (CSD) encoding techniques. Through simulation, the area and performance of an example filter are analysed using pipelined and non-pipelined modes for all three techniques. The simulation results show that, unlike in the equivalent multi-bit filters, CSD offers no advantages in single-bit sigma-delta modulated (ΔSigmaM) systems. Similarly, RBSD occupies twice the area and exhibits much poorer performance compared to a conventional 2s complement representation due to the small symbol size in single-bit systems. These results demonstrate that simple, short word length ΔSigmaM filters will be useful in greatly reducing the number of general-purpose digital multipliers in general purpose digital signal processor applications using FPGA and especially ASIC.

Fast multiplier design using redundant signed-digit numbers

A high speed multiplier design is presented using redundant binary signed-digit number representation internally while the input operands and the output product are in two's complement form. The design of a carry free redundant binary signed-digit (RBSD) adder cell is presented. The multiplication algorithm uses bit-pair recording to generate the partial products. The partial products are added in the form of a binary tree using carry free RBSD adder cells. The regular structure of these adder cells results in a multiplier design that is suitable for VLSI implementation. The increased speed is achieved through the carry free addition of partial products using redundant signed-digit numbers. The use of a recoding scheme will reduce the number of rows of partial products by a factor of two. The proposed multiplier design has a multiplication time of order O(log2 n) and area-time complexity of order O(n2 log2 n) for a word length of n.