Redundancy Addition And Removal Research Articles

A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits

Due to current technology scaling trends such as shrinking feature sizes and decreasing supply voltages, circuit reliability is becoming more susceptible to radiation-induced transient faults (soft errors). Soft errors, which have been a great concern in memories, are now a main factor in reliability degradation of logic circuits as well. In this paper, we present a systematic and integrated methodology for circuit robustness to soft errors. The proposed soft error rate (SER) reduction framework, based on redundancy addition and removal (RAR), aims at eliminating those gates with large contribution to the overall SER. Several metrics and constraints are introduced to guide the RAR-based approach toward SER reduction. Furthermore, we integrate a resizing strategy into our framework, as post-RAR additive SER optimization. The strategy can identify most critical gates to be upsized and thereby, minimize area and power overheads while maintaining a high level of soft error robustness. Experimental results show that the proposed RAR-based framework can achieve up to 70% reduction in output failure probability. On average, about 23% SER reduction is obtained with less than 4% area overhead.

ECR

Rewiring is known to be a class of logic restructuring technique that is at least equally powerful in flexibility compared to other logic transformation techniques. Especially it is wiring sensitive and is particularly useful for interconnect-based circuit synthesis processes. One of the most well-studied rewiring techniques is the ATPG-based Redundancy Addition and Removal (RAR) technique which adds a redundant alternative wire to make an originally irredundant target wire become redundant and thus removable. In this article, we propose a new Error-Cancellation-based Rewiring scheme (ECR) which can also identify non-RAR-based rewiring operations with high efficiency. In ECR scheme, it is not necessary for alternative wires to be redundant. Based on the notion of error cancellation, we analyze and reformulate the rewiring problem, and a more generalized rewiring scheme is developed to detect more rewiring cases which are not obtainable by existing schemes while it still maintains a low runtime complexity. Comparing with the most recent non-RAR rewiring tool IRRA, the total number of alternative wires found by our approach is about doubled (202%) while the CPU time used is just slightly more (8%) upon benchmarks preoptimized by ABC’s rewriting. Our experimental results also suggest that the ECR engine is more powerful than IRRA in FPGA technology mapping.

Theory of wire addition and removal in combinational Boolean networks

Let w t be a wire in a combinational Boolean network. There may exist a wire w a such that when w a is added and w t is removed, the overall circuit functionality is unchanged. Redundancy-addition-and-removal (RAR) is an efficient technique to find such a w a. The idea is to add a redundant alternative wire w a to make the target wire w t redundant. However, as long as the addition of w a together with the removal of w t does not change the overall functionality of the circuit, wires that are added and removed do not necessarily need to be redundant. This raises a question about the existence of alternative wires. Why can one wire replace another wire in a combinational Boolean network? In this paper, we analyze theoretically the existence of alternative wires and model it as an error-cancellation problem. The two existing rewiring techniques, the redundancy-addition-and-removal and the global flow optimization, are unified under the proposed generalized model.