Reduced Voltage Stress Research Articles

New Asymmetrical Modular Multilevel Inverter Topology With Reduced Number of Switches

In this article, a new single-phase multilevel inverter is introduced with a reduced number of power switches and reduced voltage stress on power switches. The proposed topology consists of four input dc sources and nine semiconductor switches (eight unidirectional and one bidirectional switch). The topology can be used for asymmetrical voltage source configuration to generate seventeen voltage levels. The extended topology is constructed by a series connection of the topology circuit to produce higher voltage levels with less voltage stress on the switches without modifying the existing structure. Comparison is made with traditional and recently introduced topologies based on the number of power switches, dc sources, total blocking voltage of switches, and gate driver circuits, to prove the proposed topology’s superiority. A simple nearest level modulation has been deployed as the switching scheme. Validation on the viability of the proposed topology has been carried out through simulation and hardware experimental setup.

A Non-Inverting High Gain DC-DC Converter With Continuous Input Current

High gain DC-DC converters are increasingly being used in solar PV and other renewable generation systems. Satisfactory steady-state and dynamic performance, along with higher efficiency, is a pre-requirement for selecting the converter for these applications. In this paper, a non-inverting high gain DC-DC boost converter has been proposed. The proposed converter has only one switch with continuous input current and reduced voltage stress across switching devices. The operating range of the duty cycle is wider, and it obtains a higher gain at a lower value of the duty cycle. Moreover, the converter has higher efficiency at a lower duty cycle while drawing a continuous input current. The continuous input current is a desirable feature of the dc-dc converter making it suitable for solar photovoltaic applications. The converter’s operation has been discussed in detail and extended to include the real circuit parameters for a practical performance evaluation. The proposed converter has been compared with other similar recently proposed converters on various performance parameters. The loss analysis for the proposed converter has also been carried out. Finally, the simulation has been validated with results from the experimental prototype.

Single-Phase Hybrid Switched-Capacitor Interleaved AC-DC Boost Converter

In this paper a single-phase boost PFC multilevel interleaved high-voltage gain based on the hybrid switched-capacitor concept is presented. The proposed converter merges interphase transformers and switched-capacitor cells to obtain current sharing and high voltage gain. These features allow for both the reduction of voltage and current stresses on the semiconductors. Furthermore, the interleaving method allows for obtaining multilevel voltages at AC terminals, thereby reducing the weight and bulk of the input inductor. PFC operation is guaranteed through both input current control and output voltage control. Both steady-state and dynamic analyses were conducted. Experimental results for a 1.25 kW, 127 V to 800 V laboratory prototype are presented and discussed.

A comprehensive review on cascaded H-bridge multilevel inverter for medium voltage high power applications

Recently, Multilevel Inverters has developed as a significant substitute in the field of high and medium power industrial applications. The multilevel inverters exhibits several intrinsic advantages over traditional two level inverters such as reduced voltage stress, reduced rating of devices, and good quality of output Power. Even though Classical topologies of multilevel inverter are still utilized in most of the key areas, the cascaded multilevel inverter is considered to be the most important power converter as it is able to produce medium power output voltages with low voltage configuration of components. The cascaded multilevel inverter with reduced number of overall switch counts is an essential objective in the emerging topologies nowadays. In this paper, a comprehensive analysis of latest cascaded multilevel inverters with reduced number of switches has been reviewed and analysed. This paper will exemplify the introduction, and the qualitative parameters of these topologies. In this paper a detailed exploration of various topologies of seven level cascaded multilevel inverter based on number of switches, number of dc sources, requirement of passive components and voltage rating of power switches has been presented with which a suitable Multilevel inverter topology can be chosen for a given applications.

A New Family of Step-Up Hybrid Switched-Capacitor Integrated Multilevel Inverter Topologies With Dual Input Voltage Sources

In the low voltage based renewable systems like PV and Fuel cell applications, the step-up of the output voltage to drive the loads is essential. For this, the integration of switched-capacitor (SC) units with the dc-ac converters will have the potential advantages like improved efficiency, optimal switching devices, small size of passive elements (L and C) as compared with traditional two-stage conversion system (dc/dc converter and dc/ac converter). This paper focuses on a new family of step-up multilevel inverter topologies with switched capacitor integration with dual input voltage sources. With the flexibility of 2 dc sources and switching capacitor circuits, four different topologies have been suggested in this paper with features of high voltage gain, reduced component count, reduced voltage stress and self-voltage balancing of the capacitor while achieving a higher number of levels. A detailed analysis of proposed multilevel inverters has been analyzed with the symmetrical and asymmetrical mode of operations and the associated gain, the number of levels, and other performance indices are presented. An in-depth study of all the topologies has been accomplished in this paper with several comparative studies in terms of components count, voltage gain and cost. The effectiveness and practicability of the suggested topology with 13 level output voltage has been explained by the experimental results obtained from a scale down prototype.

High step‐up DC–DC converter composed of quadratic boost converter and switched capacitor

This study proposes a high step-up DC–DC converter which is composed of a conventional quadratic boost converter, a switched capacitor and a coupled inductor. To reduce the number of components, the primary side of the coupled inductor is shared with the quadratic boost converter as one of its inductors. Furthermore, the output capacitor of the quadratic boost converter is divided into two capacitors and one of them is utilised in common with the switched capacitor. The converter is analysed and the obtained equations are used to compare the proposed converter with other converters which have similar structures. According to the comparisons, the proposed converter has advantages such as higher voltage gain, the lower voltage stress on the power switch and requiring a smaller inductor. In addition, the input source current is continuous and there is a common ground between the source and load. Increasing the turn ratio of the coupled inductor causes reduction of voltage stress on the power switch, diodes and capacitors. To investigate performance of the proposed converter, an 80 W prototype is built. The experiments show good accordance with the analysis and they demonstrate the high step-up capability of the proposed converter.

A novel intermediate bus converter topology for cutting edge data center applications

As new technologies emerge data centers and servers have established themselves as one of the largest and fastest growing consumers of power. While switched capacitor converter topologies have some very attractive features, namely low reliance on magnetic components and high efficiency, several critical factors have prevented their adoption in high current data center applications. The family of converters proposed are novel intermediate bus converter that demonstrates the highest performance yet achieved for 48 V to 12 V conversion with up to 2.5 kW/in <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> power density, higher than 99% peak efficiency, and 97.2% full load efficiency for 12 V/70 A output. The reduction of voltage stress across the MOSFETs as well as extremely low reliance on magnetics are the key driving factors behind this high efficiency and power density, and are achieved without a sensitive resonant design or the usage of complex control technique.

Eight‐switch CHB‐based three‐level three‐phase shunt active power filter

This study presents a reduced switch three-phase three-level H-Bridge-based shunt active power filter (SAPF) for the mitigation of current harmonics, the reduction of current unbalance and the injection of reactive power. This recommended SAPF is developed by using two H-bridge and two DC-link capacitors. Compared to the conventional three-level H Bridge-based SAPF, the eight-switch cascaded H bridge (ES-CHB)-based topology saves four semiconductor switches and one DC-link capacitor. The ES-CHB-based SAPF saves the power electronic components and reduces voltage stress across each switch by introducing a small AC capacitor in series with coupling inductor in each phase. This LC circuit also reduces the harmonic stress of SAPF by tuning at the sixth order of current harmonics. The only drawback of the suggested SAPF is the DC link voltage unbalances. To address this problem, a modified feedback control strategy is proposed in this study. The modified controller regulates the DC link voltage at the desired voltage and mitigates the DC link voltage unbalances, by using reactive power flow control and active power flow control, respectively. The performance of the suggested eight-switch three-level CHB-based SAPF is evaluated through MATLAB simulation and experimentally verified through the hardware implementation.

High‐step‐up enhanced super‐lift converter

This study proposes a new high step-up DC–DC converter based on a novel super-lift structure and coupled inductor. The energy stored in the leakage inductance of the coupled inductor is recovered to the converter output, which leads to a snubber-less operation and consequently a fewer-component, lower-cost and more-efficient converter. This feature also reduces voltage stress and the current peak of the active switch without using a snubber circuit. Analysis of continuous current mode of the proposed converter considering the leakage inductance has been demonstrated. Moreover, a comparison between several converters has been done for further information about similar research works. Experimental results such as voltage and current waveforms and efficiency curve have been presented to show the practical characteristics of the proposed converter.

A Clamped and Harmonic Injected Class-E Converter With ZVS and Reduced Voltage Stress Over Wide Range of Distance in WPT System

The inherent frequency of magnetic coupling resonance based wireless power transfer system (MCR-WPT) is up to the level of kHz or even MHz. The class-E converter with zero-voltage switching (ZVS) could eliminate the considerable switching loss, however, the high voltage stress and sensitive ZVS condition to coils distance limit its application seriously in MCR-WPT. To solve the issues, a voltage-clamped class-E converter, consisting of an auxiliary clamped circuit to decrease the voltage stress and a harmonic circuit to realize ZVS against a wide range of coils position, is proposed for the WPT system. According to the harmonic analysis, the relationship among duty cycle, input voltage, amplitudes and phases of the harmonics is obtained. Then, the design strategy for system parameters, especially for the harmonic circuit is presented, so that, ZVS could be maintained over a wide range of coils distance. Meanwhile, the efficiency analysis is also carried out, suggesting a steady high efficiency further. Three design examples with disparate harmonic parameters and ZVS ranges are presented and one of the three examples is selected to make comparison with a typical Class-E WPT system. The experimental results agree with the theoretical analysis well.

A Hybrid DC–DC Quadrupler Boost Converter for Photovoltaic Panels Integration into a DC Distribution System

This paper presents a non-isolated DC–DC boost topology with a high-voltage-gain ratio for renewable energy applications. The presented converter is suitable for converting the voltage from low-voltage sources, such as photovoltaic panels, to higher voltage levels. The proposed converter consists of a multiphase boost stage with an interleaving switching technique and a voltage multiplier cell to provide a voltage level at a reduced duty cycle. The interleaved boost stage consists of two legs and can be either fed from single or multiple voltage sources with the ability to control each source separately. The voltage multiplier cell can increase the voltage level by charging and discharging the capacitors. Several advantages are associated with the converter, such as reduced voltage stress on semiconductor elements and a scalable structure, where the number of voltage multiplier cells can be increased. The inductors in the interleaved boost stage share the input current equally, which reduces the conduction loss in the inductors. The input and the output of the converter share the same ground, and all active switches are low-side, which means no feedback or signal isolation is required. The theory of operation and steady-state analysis of the converter operating in the continuous conduction mode is presented. Components selections and efficiency analysis are presented and validated by comparative analysis and simulation results. A 0.195 kW experimental prototype was designed and implemented to convert the voltage from 20 V input source to 400 V output load, at 50 kHz. The test results show a high-performance of the converter as the maximum efficiency point is above 97%.

Switched‐capacitor‐based boost multilevel inverter topology with higher voltage gain

This study proposes a new switched-capacitor-based multilevel inverter topology with a single dc voltage source. The proposed topology finds its suitability for renewable energy applications with low voltage. Seven-level (7L) output voltage is achieved across the load with triple-voltage gain employing 2 capacitors and 12 switches. Self-voltage balancing of capacitor voltages, parallel operation of capacitors during discharging mode, reduced voltage stress, and bipolar output voltage generation without using backend H-bridge are the major features of the proposed topology. Furthermore, a generalised structure of the proposed topology has also been discussed here. A comparison with other similar topologies with single-source 7L configuration has been carried out to show the advantages of the proposed topology with reduced switch count. Experimental results have been provided to verify the performance of the proposed topology with different operating conditions.

High step‐down dc–dc converter with low voltage stress and wide soft‐switching range

In this study, the integration of buck converter with Cuk converter to achieve a non-isolated high step-down dc–dc converter is investigated. Also, a soft-switching cell is modified and used in the integrated converter to provide zero current switching and zero voltage switching condition for the converter switches at turn-on and turn-off, respectively. The auxiliary cell also eliminates the reverse recovery problem of the converter diodes. As a result, a high efficiency high step-down converter with reduced voltage stress for semiconductor components is derived. The analysis, operational principle and design considerations of the proposed converter are discussed in this study. The accuracy of the converter operation is verified by a 200 W, 155 V-to-24 V laboratory prototype.

Reduced voltage stress hybrid multilevel inverter using optimised predictive control

This study presents a hybrid multilevel inverter (HMLI), capable of generating 19 voltage levels using a single DC voltage source. The peak inverse voltage of all the switches is restrained within the input DC source voltage in the proposed HMLI, which requires only three capacitors and 15 switches to achieve 19 voltage levels. In the proposed HMLI, one of the capacitors is self-balanced, while the other two capacitors are balanced using a modified finite control set model predictive control (MFCS-MPC). The proposed MFCS-MPC reduces the computation time considerably without affecting the performance of the system. The proposed HMLI is compared with some other HMLI topologies to show its merits in terms of active and passive components. Finally, the steady-state and dynamic performance of the proposed topology and its control algorithm is validated through simulation and experimentation for a 1 kW prototype.

An Improved Three-Phase Buck Rectifier With Low Voltage Stress on Switching Devices

An improved three-phase buck rectifier (3ph-BR) with low voltage stress on switching devices is proposed in this letter. In the conventional 3ph-BR, the voltage stress on MOSFET s is higher than the amplitude of input phase voltage. However, in the proposed 3ph-BR, the voltage stress on MOSFET s is lower than the amplitude of input phase voltage, which results in reduction of voltage stress on MOSFET s. Therefore, the cost-efficient and low voltage rating MOSFET s with low on-resistance can be utilized, which makes the proposed 3ph-BR suitable for applications that require high-efficiency and high-density. A 1.5-kW experimental prototype of the proposed rectifier is built to verify the analysis results.

DesignandSimulation of High-Efficiency High Gain non Isolated Interleaved DC-DC Converter with Reduced Voltage Stress on the Devices

DesignandSimulation of High-Efficiency High Gain non Isolated Interleaved DC-DC Converter with Reduced Voltage Stress on the Devices

DesignandSimulation of High-Efficiency High Gain non Isolated Interleaved DC-DC Converter with Reduced Voltage Stress on the Devices

In this paper, a non-isolated two interleaved modified step up KY Converter is analyzed and designed, whose efficiency,the voltage conversion ratio is high. There are various types of non -isolated converters such as buck-boost, Cuk, SEPIC, ZETA converters, etc but the voltage gain of these converters is less compare to the proposed interleaved KY converters. The voltage gain, efficiency of the proposed converter is enhanced compared to the previous converters. The voltage stress on semi-conductor devices and the ripple in the input current is reduced because of this interleaving technique. Switches with low on-state resistance are used due to which the conduction losses are reduced. Steady-state analysis and the operating principle are studied in continuous conduction mode (CCM) at ideal conditions. Simulation is also carried out in MATLAB/Simulink for the proposed interleaved KY converter.

A topology of coupled inductor DC–DC converter with large conversion ratio and reduced voltage stress on semiconductors

This study presents a high boost DC–DC converter, integrates voltage multiplier cell, voltage lift capacitor, and coupled-inductor techniques to achieve a high-voltage gain. The proposed topology has the capability of extension without utilising any additional winding for a very large voltage conversion ratio. With utilising a passive clamp circuit and without requiring higher duty cycle values, the suggested converter obtains a large conversion ratio, low conduction losses, and reduced voltage stress of semiconductors with a steady value for the whole range of duty cycle. The converter operation principle is discussed and its steady-state operation is analysed in detail. Also, theoretic efficiency calculation and design guidelines of the topology are explained. Then, the proposed DC–DC converter is compared with similar configurations to indicate its advantages. Eventually, the validity of theoretic analysis is verified using experimental measurement results of the implemented prototype with a power rating of 226 W.

A Family of Transformer-Less Single-Switch Dual-Inductor High Voltage Gain Boost Converters With Reduced Voltage and Current Stresses

A family of transformer-less single-switch dual-inductor high voltage gain boost converters is proposed in this article. The proposed configurations can realize high voltage gain with low voltage and current stresses. The voltage gain of the proposed converters is analogous to the switched inductor boost converter; therefore, the proposed boost converters are suitable for high gain applications. The proposed family of converters has low component counts and reduced voltage stress on devices compared to three typical transformer-less single-switch high voltage gain converters including switched inductor boost converter, quadratic boost converter, and quasi- Z -source boost converter. Moreover, the current stress of the front-end diode and the rear-end inductor is also relatively low. Therefore, the conversion efficiency is enhanced while keeping the cost low. The operation principles and steady-state characteristics analysis of the proposed converters under the inductor current continuous conduction mode and continuous bidirectional conduction mode are discussed in detail. A prototype of 300 V, 250 W/100 kHz is developed to verify the performance of the proposed converter. The experimental results substantiate the effectiveness and advantages. The prototype achieves a peak efficiency of 97.5 $\%$ .

Soft-Switched Ultrahigh Gain DC–DC Converter With Voltage Multiplier Cell for DC Microgrid

In this article, a soft-switched modular nonisolated converter is proposed for distributed generation systems. By integrating flyback energy delivering circuit to the interleaved boost converter, ultrahigh-voltage gain and high efficiency are achieved with reduced duty ratio. Cockcroft-Walton based multiplier cell extensively reduces voltage stress on the active switches. Voltage spikes across mosfets caused by leakage inductance and interconnection of primary-secondary windings are alleviated by adjoining the active switch based auxiliary circuit. Thus, low voltage rating switches (small R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds(on)</sub> ) are employed. Furthermore, the clamp circuit realizes wide-load-range zero-voltage switching (ZVS) turn-on and, reduced falling current magnitudes ensures low turn-off losses for all the mosftets. Also, leakage-energy is recycled to the load. Indeed, leakage-energy effectively limits the rate of fall-current (di <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</sub> /dt) through power diodes and alleviates the reverse-recovery problem by turning-off them with zero-current switching. Furthermore, during turn-on, ZVS is achieved for all the diodes. Thus, voltage spikes across the diodes are suppressed without needing any snubber. Minimized voltage stresses, lowered on-state and switching losses of the semiconductor devices, altogether, improves the efficiency. A 600-W prototype working at 100 kHz is developed in the laboratory to validate the design analysis. Measured efficiency at rated-load is 95.81% and maximum efficiency is 96.65%.