Reduced Switch Topology Research Articles

Enhancing power conversion efficiency in five-level multilevel inverters using reduced switch topology

This paper presents extensive research on improving the power conversion efficiency of five-level multilevel inverters (MLIs) by utilizing a reduced switch topology. MLIs have received an abundance of focus because of their ability to generate high-quality output waveforms and have better harmonic outcomes than traditional two-level inverters. The high number of switches in MLIs, on the other hand, can result in increased power losses and lower overall efficiency. In this paper, a novel reduced switch topology for five-level MLIs, which is having five switches is proposed with the aim of minimizing power losses while preserving superior performance due to lesser number of switches. To achieve efficient power conversion, the proposed topology employs advanced pulse width modulation control strategies and optimized switching patterns. The simulation results show that the minimized switch topology improves the power conversion efficiency of the five-level MLI, resulting in lower losses and better overall system performance. The total harmonic distortion (THD) value of the output current has been reduced to 7.12% and the efficiency has been achieved to 96.92%. The findings of this investigation help to advance MLI technology, allowing for more efficient and reliable power conversion in a variety of applications such as renewable energy systems, electric vehicles, and industrial drives.

Hybrid Optimization Based Harmonic Minimization in Three Phase Multilevel Inverter With Reduced Switch Topology

Hybrid Optimization Based Harmonic Minimization in Three Phase Multilevel Inverter With Reduced Switch Topology

A Review on Multilevel Converters for Efficient Integration of Battery Systems in Stationary Applications

Recently, multilevel converters (MLCs) have gained significant attention for stationary applications, including static compensators, industrial drives, and utility-grid interfaces for renewable energy sources. Compared to two-level voltage-source inverters (VSI) MLCs feature high-quality AC voltage with reduced harmonic content despite the lower switching frequency of the semiconductor devices. On the DC side, MLCs can integrate multiple isolated/non-isolated battery modules instead of a single battery pack. This helps to keep the system in service in case of a malfunction of one or more battery modules, as well as active balancing among the modules, a feature not possible with two-level VSI. In general, MLCs can be classified into two types: (i) two-port MLCs, which provide a single interface to connect with the battery pack, and (ii) multiport MLCs, which provide multiple interfaces to allow connection at the module or cell level. The classical topologies of both MLC types (e.g., neutral point clamped, flying capacitor, cascaded bridge) face limitations due to the high switch count. Consequently, many hybrid and reduced-switch topologies are reported in the literature. This paper presents a critical overview of both classical and recently reported MLC topologies and offers a better insight of MLC operation for grid-connected and standalone applications. In addition, the analysis thoroughly assesses various high-level control and modulation strategies while considering active balancing among the battery modules. Other salient features such as balancing speed during offtake/grid-injection mode and fault-ride-through capability are also incorporated. In conclusion, the key findings are summarized for a better understanding of the present and future integration of battery systems in stationary applications.

Low and High Frequency Control Strategy for Asymmetrically Switched Cascaded Multilevel Inverter

This paper proposes low and high frequency control techniques for asymmetrically switched cascaded multilevel inverters (MLI). Initially, Low frequency-based switching angle calculation methods are proposed for the suggested topology. Then high frequency-based Multi-carrier pulse width modulation (MCPWM) techniques are used to control the switching states of multilevel inverters for asymmetrical sources. The proposed multilevel inverter is a reduced switch topology with a modular version realized. From the modular version of the topology, three asymmetrically switched (7, 13 & 21) levels are simulated by MATLAB/Simulink environment and comparisons among themselves are also considered according to method of switching techniques and power quality, i.e. total harmonic distortion (THD). The designed inverters are recommended for photovoltaic power generation as they are suitable to integrate separate DC power sources. The inverters are designed and simulated with a proper simulation environment and experimentally verified through hardware in loop (HIL) using OPAL-RT (OP-5600) testbed.

Mitigation of Circulating Bearing Current in Induction Motor Drive Using Modified ANN Based MRAS for Traction Application

Induction motors are popularly used in various applications because of the proposed modest construction, substantiated process, and limited size of specific power. The traditional AC traction drives are experimentally analyzed. There is a high circulating current due to the high Common-Mode Voltage (CMV). The high Circulating Bearing Current (CBC) is a major problem in conventional two-level voltage source inverter fed parallel-connected sensor-based induction motors for traction applications. A sensorless method is well known for shrinking costs and enhancing the reliability of an induction motor drive. The modified artificial neural network-based model reference adaptive system is designed to realize speed estimation methods for the sensorless drive. Four dissimilar multilevel inverter network topologies are being implemented to reduce CBC in the proposed sensorless traction motor drives. The multilevel inverter types are T-bridge, Neutral Point Clamped Inverter (NPC), cascaded H-bridge, and modified reduced switch topologies. The four methods are compared, and the best method has been identified in terms of 80% less CMV compared to the conventional one. The modified cascaded H-bridge inverter reduces the CBC of the proposed artificial neural network-based parallel connected induction motor; it is 50% compared to the conventional method. The CBC of the modified method is analyzed and associated with the traditional method. Finally, the parallel-connected induction motor traction drive hardware is implemented, and the performance is analyzed.

Performance Estimation of Adaptive Fuzzy Logic Speed Controller for Reduced Switch BLDC Motor Drive

This article deals with the implementation of an adaptive fuzzy logic based reduced switch brushless DC motor drive. In topological view, the cost of the system chiefly depends upon the power semiconductor switches. Hence switch reduction concept is adapted in this paper. The operating principle, switching sequence formulation of reduced switch topology is presented. An intelligent system for reduced switch BLDC drive is designed and tested for different load conditions. Simulation results as well as comparative performance with conventional controllers are presented and discussed. The parameters such as rise time and steady state error are observed. The effectiveness and robustness of the reduced switch BLDC drive for variable speed applications is demonstrated. The rise time and steady state error of the proposed system is improved about an average of nearly 60% and 30% respectively compared to other controllers.

WITHDRAWN: An experimental approach of DVR for relieving voltage dip and voltage swells

Abstract Based on recent power quality studies, voltage dip and swells in the medium and low voltage distribution grid are regarded as the most frequent form of power quality problems. Their effect is serious on sensitive loads. The effect varies from load disturbances to major economic losses to millions of dollars. Different solutions have been developed to defend sensitive loads against such disturbances, but the most powerful and efficient solution is considered to be the DVR..In this paper, the hardware setup of DVR to relieve the voltage dip and swell has implemented by the use of the micro-controller and control circuit for the H-bridge inverter. The system suggested in the article provided has a limited variety of changing devices that decreases the intricacy of the circuit as well as using the microcontroller (LPC2148) to use a simple control circuit. The multi-level inverters give almost sinusoidal result waveform, the result exists with polished harmonic account and switching losses that are less than the traditional level inverter, and thus smaller filter dimension is needed. Regular cascaded MLI as well as various other current7-level reduced switch topologies making use of carrier-based PWM methods, the performance top quality in terms of THD, and also switching losses of the brand-new MLI compared.

Reduced Switch Multilevel Inverter based STATCOM

This paper presents an application of reduced switch multilevel inverter topology to STACOM. This topology consists of basic unit in which two switches are connected in series and one H-bridge unit. Multilevel inverter is beneficial in terms of reliability and improved output quality. Multilevel inverter have only drawback of higher number of switches. This reduced switch topology has less number of switches as compared to conventional Cascaded H Bridge Inverter. Compared to direct control method, indirect control method is simple but due to fast response and precise control, direct current control method is quite effective. In this work STACOM is implemented to improve the Power factor of the power system. An extensive digital simulation of the recommended STATCOM and its controller is carried out using MATLAB/SIMULINK software to study system performance. Simulation results prove that using Direct current control technique overall power factor is improved.

Design analysis of high level inverter with EANFIS controller for grid connected PV system

For providing better reliability and getting minimal harmonics, multilevel inverters are commonly employed in grid connected photovoltaic systems. This paper presents 27 level inverter with reduced switch topology to get better reliability with low harmonics. This inverter performance completely relies on EANFIS controller which is the combination of ANFIS and Emperor Penguin Optimization (EPO) algorithm. Working procedure of ANFIS will be optimized by EPO to make us easy to deal MLI switching angle and produce harmonic-less control voltage. EPO provides efficient result by means of computational complexity, time and space complexity. In our work, this is the main reason to select EPO for optimizing ANFIS controller. The proposed work will be implemented in Simulink working environment. Resultant outcomes like inverter output, controller output and THD analysis will be compared with recently developed existing works.

Unified power quality conditioner with reduced switch topology for distributed networks

A unified power quality conditioner (UPQC) is a combination of shunt and series converter used to mitigate various power quality issues. In this work the shunt and series converters are designed with reduced number of switches. The new UPQC with reduced switches is controlled using SRF based Carrier Double Zero Sequence Signal Modulation (CDZSSM) technique to mitigate the various power quality issues like voltage sag, current ripples and Total Harmonic Distortion in voltage and current waveforms. This reduced switch UPQC with CDZSSM control inherits all the merits of the conventional UPQC system, but the proposed UPQC system has better utilization of DC link voltage and moreover the voltage stresses across the switches are reduced. The results obtained from simulation and hardware of the reduced switch UPQC are compared and presented.

Investigation of modified multilevel inverter topology for PV system

Multilevel inverters become an alternative for high power and medium voltage applications in recent years. Multilevel inverters(MLI) are basically classified as Diode Clamped Multilevel inverter, Flying Capacitor Multilevel inverter, Cascaded H Bridge Multilevel Inverter (CHBMLI). The CHBMLI topology which consists of a series of H bridge unit with separate dc sources is mostly prefered to generate higher voltage levels, as it requires fewer components compared to the other topologies. As the level increases, the switching device requirement will be more and the circuit becomes large with this topology. To overcome this and to produce high quality output, reduced switch count topologies are the main focus in recent research.The reduced switch count structures are based on bidirectional switches, modified form of the structures, polarity and level generation based structure, reduced switch structures and hybrid topology structure. This paper proposes a three phase Modified Multilevel Inverter (MMLI) topology with reduced switch count for nine level and the topology is analyzed using different Pulse Width Modulation (PWM) technique. The proposed MLI structure consists of an H bridge unit with voltage conversion cell for each phase. It requires 24 switches for a 3Ф nine level inverter with eight switches per phase compared to 48 switches in CHBMLI. The Total Harmonic Distortion (THD) level of this topology is examined with the PWM techniques for symmetric and asymmetric DC voltage sources. THD results of the proposed MLI are compared with other reduced switch topology structure. The comparison result indicates that the proposed topology shows better harmonic level and reduced switches compared to that structure. A prototype of the proposed topology is built and is tested to validate with the simulation results. Simulation and experimental results show that the proposed topology produces a minimum harmonic level with fewer components.

A Reduced Switch Hybrid Multilevel Unidirectional Rectifier

Nonregenerative pulsewidth-modulated (PWM) rectifiers are increasingly being considered for applications, where the power flow is unidirectional, such as power supplies for telecommunications, X-ray, the machine-side converter for wind energy conversion systems, etc. They use fewer active switches, which increase their power density and reduce cost. This paper proposes a novel reduced switch topology for a multilevel (five-level or higher) nonregenerative PWM rectifier. It uses only four controlled switches and eight diodes per phase for a five-level rectifier. Half of the diodes are naturally commutated (zero current switching) at the line frequency, which reduces switching losses. This topology has several other advantages compared to similar topologies reported in the literature, such as minimum voltage stress across the devices, elimination of transient voltage-balancing snubbers, no extra hardware for balancing the flying capacitors, the dc-link mid-point voltage, etc. In this paper, switching cycle average modeling and the carrier-based modulation strategy for this rectifier are also presented to maintain a balanced dc link and to regulate flying capacitor voltages, while achieving unity displacement factor at the rectifier input terminals. The overall performance of the rectifier is verified by experimental results.

A Reduced Switch AC-AC Converter with the Application of D-STATCOM and Induction Motor Drive

In this paper, a reduced switch AC-DC-AC converter is used as a distribution static compensator (DSTATCOM) and induction motor drive. The AC-DC-AC nine switch converter (NSC) is a reduced switch topology of conventional 12-switch back to back converter. With a 25% reduced switch count, NSC has lower losses when operated at constant frequency mode compared to twelve switch converter (TSC). The idea is to operate NSC input terminal as an active front-end rectifier to mimic synchronous generator (SG) operation. The induction motor is connected at the output of the NSC for irrigation application where no speed regulation is required. In distribution generation (DG), a large capacitor bank is used to deliver required reactive power. This may lead to over-voltage at the point of common coupling (PCC) when the load is turned off. To manage reactive power transfer at PCC, a control scheme is developed for NSC such that it can absorb or deliver reactive power with induction motor drive. Similar to SG, V-curve and inverted V-curve is plotted. The simulation and hardware results prove the feasibility of the proposed system.

Hybrid optimization algorithm applied for selective harmonic elimination in multilevel inverter with reduced switch topology

This paper presents, ant colony optimization based hybrid algorithm for selective harmonic elimination in single phase seven level multilevel inverter with reduced switches. For high power and high voltage applications, multilevel structure with selective harmonic elimination (SHE) modulation scheme is used. The output voltage of multilevel inverter contains fundamental component along with harmonics. SHE technique aims to solve non-linear transcendental equations maintaining the fundamental harmonic component to its desired value and to eliminate lower order odd harmonics. Many optimization algorithms have been implemented to solve this problem. But these algorithms are complicated and time consuming. The Newton–Raphson algorithm is also very convergent for solving these non-linear equations. The main disadvantage of this method is, it requires strong initial guess. To overcome these drawbacks, hybrid optimization algorithm is used in this paper. This algorithm is performed in two stages, during first stage ant colony optimization has been run and in second stage the solutions obtained from ACO is used as a initial guess for Newton–Raphson algorithm which confirms the exact converged solution. Thus the drawback of Newton’s method i.e. requirement of good initial guess is overcomed by proposed hybrid algorithm. The MATLAB/SlMULINK software is used for comprehensive simulation of seven-level inverter. Experimental results validate the simulated results.

A Single Phase Grid Connected Hybrid Multilevel Inverter for Interfacing Photo-voltaic System

Abstract This paper introduces a new single phase hybrid multilevel inverter with a minimum number of switches for a Photovoltaic application. A Perturb and observe maximum power point tracking is used for tracking maximum power from solar panel. A boost converter is used for boosting the generated voltage because proposed inverter operates at the asymmetric condition. The proposed inverter is the combination of reduced switch topology and cascaded H-Bridge topology. Two types of Phase Disposition carrier arrangement with sinusoidal reference is utilized for generating the gating pulses for proposed inverter. It generates a 15-level output voltage with 8.12% of total harmonic distortion.

Finite Control Set Model Predictive Current Control for a Cascaded Multilevel Inverter

In this paper, a Finite Control Set Model Predictive Control (FCS-MPC) for a five level cascaded multilevel inverter (CMLI) with reduced switch topology is proposed. Five switches are used here instead of conventionally used eight switches. The main contribution of this paper is to make the MPC controller work for the reduced switch topology using only 19 voltage vectors in place of conventional 61 voltage vectors for a five level CMLI. This simplifies the execution of the MPC algorithm, paving a way for the significant reduction in the computational time. The controller makes use of the excellent ability of MPC to multitask, by adding one more objective which is to reduce the average switching frequency in addition to controlling the load current. This is especially important, since switching losses and therefore switching frequency is significant for high-power applications. The trade-off of this MPC is that the current is not as smooth as the 61 vector scheme, but well within the limits of IEEE standards. The results shown prove that this MPC works well in steady state and dynamic conditions too.

Analysis of Reduced Switch Topology Multilevel Inverter with Different Pulse Width Modulation Technique and Its Application with DSTATCOM

Multilevel inverter has played a vital role in medium and high power applications in the recent years. In this paper, Reduced Switch Count Multi Level Inverter structure (RSCMLI) topology is presented with different pulse width modulation techniques. The harmonic level analysis is carried out for the reduced switch count multilevel inverter with the different PWM technique such as with Alternate Phase Opposition Disposition (APOD) method, In Phase Disposition (IPD) method and multi reference pulse width modulation method for five level, seven level , nine level and eleven level inverter. The simulation results are compared with the cascaded H Bridge Multi Level Inverter (CHBMLI). The nine level RSCMLI inverter with APOD method is used for the Distribution Static Synchronous Compensator (DSTATCOM) application in the nonlinear load connected system for power factor improvement. The result shows that the harmonic level and the number of switches required for RSCMLI is reduced compared to CHBMLI. RSCMLI employed in DSTATCOM improves the power factor and harmonic level of the system when it is connected to the nonlinear load.

A low cost single phase grid connected reduced switch PV inverter based on Time Frame Switching Scheme

Abstract The domain of Grid Connected Inverter (GCI) and reduced switch topology in multi-level inverter (MLI) are gaining its attention in terms of reducing cost and optimization. For such a motivation, many researchers are addressing their efforts in proposing new MLI topologies or in modifying the existing ones, aiming at improving the quality of the energy available at the inverter terminals. The proposed split capacitor based topology uses only a single dc supply to generate any required output levels. The split capacitors are considered to obtain stepped output by adopting a Time Frame based Switching Scheme (TFSS). The numbers of semiconductor switches are reduced with an improvement in the harmonic factor. The power output is then filtered using passive inductor component and then synchronized to feed the grid power system. The result of the proposed topology is verified by Matlab/Simulink simulation and hardware implementation using a dsPIC30F4011 controller. The simulation and experimental results are compared to previous studies. The proposed scheme offers an excellent performance with significant result in lowest THD obtained and also enables the inverter to operate under unhinged PV conditions comprehensively.

Application Criteria for Nine-Switch Power Conversion Systems with Improved Thermal Performance

Nine-switch converter is a reduced-switch equivalence of the widely used 12-switch back-to-back converter. Like other reduced-switch topologies, the nine-switch converter experiences operating constraints, which may limit its efficiency. This is, however, not universal, meaning losses of the nine-switch converter can at times be lower than the 12-switch back-to-back converter. The scope of this paper is, thus, to identify application criteria for the nine-switch converter, which upon met, will lead to lower conduction and hence total losses. Loss distribution among switches of the nine-switch converter is also investigated, since it can greatly influence reliability of the overall converter. Experimental results obtained have promptly justified the analytical reasoning formulated.

A Novel Ten-Switch Topology for Unified Power Quality Conditioner

This paper proposes a new topological configuration for a unified power quality conditioner (UPQC). Generally, the power structure of the three-phase three-wire UPQC consists of two back-to-back connected six-switch inverters. For this configuration, out of 12 switches, six of the series inverter switches will be underutilized most of the time. To improve the semiconductor utilization and consequently to reduce the total switch count, this paper proposes a new reduced switch topology for the UPQC. The proposed topology is realized using only ten switches and retains all the performance merits of the 12-switch UPQC while minimizing its underutilization without increasing the switch VA rating. The paper provides a detailed analytical study and evaluation by comparing the proposed topology with the twelve- and nine-switch-based UPQC system configurations. The feasibility of the proposed topology is validated through experimental investigation.