Reduced Pressure Chemical Vapor Deposition Research Articles

Low-temperature epitaxial SiGe:P for gate-all-around n-channel metal-oxide-semiconductor devices

This study investigates the viability of Si1−x Ge x :P (x ≤ 0.3) as a novel source/drain material for n-channel Metal-Oxide-Semiconductor for Gate-All-Around (GAA) transistors, addressing the challenges posed by the evolving semiconductor technology. Utilizing a reduced-pressure chemical vapor deposition system, undoped SiGe with low Ge contents were grown at temperatures of ≤500 °C. The addition and optimization of phosphorous doping using phosphine results in improved surface morphology and increased active carrier concentration. The study compares Si1−x Ge x :P with different silicon precursors and temperatures, emphasizing the potential for maintaining high growth rates at lower temperatures when using Si3H8. Ti/Si1−x Ge x :P stacks reveal a promising reduction in contact resistivity with decreasing the Ge content, particularly when incorporating thin Si:P cap layers at the Ti/Si1−x Ge x :P interface. This comprehensive study highlights the potential of Si1−x Ge x :P as an alternative material for advanced GAA transistor technologies, offering improved mobility and meeting the thermal budget requirements.

Evaluation of Thermal Transport Characteristics of Three-Dimensional Self-Ordered Multilayered Silicon-Germanium Nanodots

1. Background and purpose Silicon-germanium (SiGe) alloys have much lower thermal conductivity than Si and Ge single crystals and are expected to be candidates for next-generation thermoelectric device materials of internet of things society. It is important to achieve both high carrier mobility and low thermal conductivity on the basis of the dimensionless figure of merit [1]. There are several studies on the thermoelectric properties of SiGe with low-dimensional structures such as superlattice and nanodots [2,3] to dramatically decrease thermal conductivity. However, the relationship between the nanoscale thermal properties and the phonon scattering mechanism of self-ordered multilayer SiGe nanodots with high uniformity grown by Stranski-Krastanov [4] mode is unclear. In this study, we demonstrated the thermal transport characteristics of the self-ordered multilayer SiGe nanodots. 2. Experiments Si/SiGe superlattice and nanodots samples were fabricated by reduced pressure chemical vapor deposition. We set to 20 cycles of Si0.65Ge0.35 / Si superlattice, the staggered Si0.65Ge0.35 nanodots (alternately stacked) and the dot-on-dot Si0.65Ge0.35 nanodots (vertically stacked) by changing growth temperature and precursors for Si spacer growth [4], as shown in Fig. 1. Thermal properties were evaluated by the Time Domain Thermoreflectance (TDTR) method. The strain states and Ge fraction were evaluated by Raman spectroscopy. The focal length and wavenumber resolution of the Raman spectrometer were 2,000 mm and 0.1 cm-1, respectively. The excitation light source was a green laser (wavelength: 532 nm). We obtained the Raman spectra of Si-Si, Si-Ge, and Ge-Ge vibrational modes derived from the SiGe regions. 3. Results and discussion Figure 2 shows the thermal conductivity for the SiGe region of the superlattice and nanodots (dot-on-dot and staggered structures) obtained by TDTR method. We found that the SiGe nanodots with the dot-on-dot structure have the highest thermal conductivity, while the SiGe nanodots with the staggered structure and SiGe superlattice have almost the same thermal conductivity. We consider that the heat flow easily penetrates from the top (surface) to the bottom (Si substrate interface) in the dot-on-dot structures. On the other hand, it is possible that the staggered SiGe nanodots can play a sufficient role as a phonon scatterer compared to the dot-on-dot structures since the superlattice structure and the staggered SiGe nanodots have almost the same thermal properties. In conclusion, we demonstrated the possibility of controlling phonon scattering by changing the arrangement of the self-ordered multilayer SiGe nanodots. Acknowledgement This work was supported by JSPS KAKENHI Grant Number 21K14201, Japan.

High-performance GeSi/Ge multi-quantum well photodetector on a Ge-buffered Si substrate.

This work demonstrates a high-performance photodetector with a 4-cycle Ge0.86Si0.14/Ge multi-quantum well (MQW) structure grown by reduced pressure chemical vapor deposition techniques on a Ge-buffered Si (100) substrate. At -1 V bias, the dark current density of the fabricated PIN mesa devices is as low as 3 mA/cm2, and the optical responsivities are 0.51 and 0.17 A/W at 1310 and 1550 nm, respectively, corresponding to the cutoff wavelength of 1620 nm. At the same time, the device has good high-power performance and continuous repeatable light response. On the other hand, the temperature coefficient of resistance (TCR) of the device is as high as -5.18%/K, surpassing all commercial thermal detectors. These results indicate that the CMOS-compatible and low-cost Ge0.86Si0.14/Ge multilayer structure is promising for short-wave infrared and uncooled infrared imaging.

Selective Epitaxy of Germanium on silicon for the fabrication of CMOS compatible short-wavelength infrared photodetectors

Here we present the selective epitaxial growth of Ge on Si using reduced pressure chemical vapor deposition on SiO2/Si solid masks realized on 200 mm Si wafers, aiming at manufacturing integrated visible/short-wavelength infrared photodetectors. By a suitable choice of the reactants and of the process conditions, we demonstrated highly selective and pattern-independent growth of Ge microstructure featuring high crystalline quality. The Ge “patches” show a distinct faceting, with a flat top (001) facet and low energy facets such as e.g. {113} and {103} at their sidewalls, independently on their size. Interdiffusion of Si in to the Ge microcrystals is limited to an extension of ∼20 nm from the heterointerface. The Ge patches resulted to be plastically relaxed with threading dislocation density values better or on par than those observed in continuous two-dimensional Ge/Si epilayer in the low 107 cm−2 range. A residual tensile strain was observed for patches with size >10 μm, due to elastic thermal strain accumulation, as confirmed by μ-Raman spectroscopy and μ-photoluminescence characterization. Polarization-dependent Raman mapping highlights the strain distribution associated to the tridimensional shape. On this material, Ge photodiodes were fabricated and characterized, showing promising optoelectronic performances.

Highly oriented crystalline si on epitaxial Gd2O3/Si(111) substrate using low-cost Radio Frequency sputtering for Silicon on Insulator application

Silicon-on-Insulator (SOI) technology has been the center of attraction with the advancement in Radio Frequency (RF) technology and the advent of Internet-of-Things due to its low-power operation with reduced parasitic and short-channel effects. However, the state-of-the-art smart-cut method used for the SOI wafer is costly. Alternatively, the notion of using the Si channel layer on epitaxial rare-earth oxide has been proposed. In literature, the existing techniques used to achieve the same, such as Molecular beam Epitaxy or reduced-pressure chemical vapor deposition technique, are either costly or non-high-volume manufacturable. In this context, we propose a method to fabricate the highly oriented crystalline Si(111) channel layer (Top-Si) on an epitaxial Gd2O3/Si(111) virtual substrate (SOXI) utilizing the solid phase epitaxy using the high-volume manufacturing friendly (HVM), low-cost RF magnetron sputtering technique. First, we have shown the multicrystalline Si and epitaxial Gd2O3 layer grown on Si(111) substrate, as confirmed using high-resolution X-ray diffraction (HRXRD) and Transmission Electron Microscopy (TEM). Second, we investigated the impact of rapid thermal annealing at 850 °C on the heterostructure using HRXRD and TEM. It is observed that the high-temperature annealing transforms the Top-Si layer into the highly oriented crystalline Si(111) layer by fusing smaller grains towards larger grains. Hence, we demonstrate a low-cost, HVM-friendly technique for the fabrication of SOXI wafers.

Epitaxial growth of high-quality Ge layers on Si with Ge2H6 under UHV-CVD conditions

Epitaxial growth of Ge films on Si(100) substrates has been studied under ultra-high vacuum chemical vapor deposition (CVD) conditions by using digermane (Ge2H6) as the precursor. It was found out that high quality layers with thicknesses beyond 500 nm could be produced at complementary metal–oxide–semiconductor compatible conditions, demonstrating low defect density, sharp and narrow x-ray diffraction peaks, as well as room temperature photoluminescence around 1550 nm. The surface roughness values are comparable to prior reduced pressure CVD results at similar growth temperatures. By employing higher growth temperatures, growth rates are significantly enhanced, resulting in much thicker layers beyond 2000 nm. Smoother sample surface could also be obtained, yielding a state-of-the-art surface root-mean-square roughness value of 0.34 nm for the as-grown sample. At the same time, after being annealed at 750 °C for 20 min, the full width at half maximum (FWHM) of x-ray diffraction 004 rocking curve spectrum of the Ge layer is as low as 88 arcseconds, which stands the best among all Ge/Si samples. The current work has provided important reference for Ge/Si growth with Ge2H6 in low pressure regime and solidified material grounding for Ge-based optoelectronics and Si photonics.

Nuclear Spin-Depleted, Isotopically Enriched 70 Ge/28 Si70 Ge Quantum Wells.

The p-symmetry of the hole wavefunction is associated with a weaker hyperfine interaction, which makes hole spin qubits attractive candidates to implement quantum processors. However, recent studies demonstrate that hole qubits are still very sensitive to nuclear spin bath, thus highlighting the need for nuclear spin-free germanium (Ge) qubits to suppress this decoherence channel. Herein, this work demonstrates the epitaxial growth of 73 Ge- and 29 Si-depleted, isotopically enriched 70 Ge/silicon-germanium (SiGe) quantum wells. The growth is achieved by reduced pressure chemical vapor deposition using isotopically purified monogermane 70 GeH4 and monosilane 28 SiH4 with an isotopic purity higher than 99.9% and 99.99%, respectively. The quantum wells consist of a series of 70 Ge/SiGe heterostructures grown on Si wafers. The isotopic purity is investigated using atom probe tomography (APT) following an analytical procedure addressing the discrepancies caused by the overlap of isotope peaks in mass spectra. The nuclear spin background is found to be sensitive to the growth conditions with the lowest concentration of 73 Ge and 29 Si is below 0.01% in the Ge well and SiGe barriers. The measured average distance between nuclear spins reaches 3-4 nm in 70 Ge/28 Si70 Ge, which is an order of magnitude larger than in natural Ge/SiGe heterostructures.The spread of the hole wavefunction and the residual nuclear spin background in APT voluminals comparable to the size of realistic quantum dots are also discussed.

Multiple SiGe/Si layers epitaxy and SiGe selective etching for vertically stacked DRAM

Fifteen periods of Si/Si0.7Ge0.3 multilayers (MLs) with various SiGe thicknesses are grown on a 200 mm Si substrate using reduced pressure chemical vapor deposition (RPCVD). Several methods were utilized to characterize and analyze the ML structures. The high resolution transmission electron microscopy (HRTEM) results show that the ML structure with 20 nm Si0.7Ge0.3 features the best crystal quality and no defects are observed. Stacked Si0.7Ge0.3 ML structures etched by three different methods were carried out and compared, and the results show that they have different selectivities and morphologies. In this work, the fabrication process influences on Si/SiGe MLs are studied and there are no significant effects on the Si layers, which are the channels in lateral gate all around field effect transistor (L-GAAFET) devices. For vertically-stacked dynamic random access memory (VS-DRAM), it is necessary to consider the dislocation caused by strain accumulation and stress release after the number of stacked layers exceeds the critical thickness. These results pave the way for the manufacture of high-performance multivertical-stacked Si nanowires, nanosheet L-GAAFETs, and DRAM devices.

Interface Investigation on SiGe/Si Multilayer Structures: Influence of Different Epitaxial Process Conditions.

SiGe/Si multilayer is the core structure of the active area of gate-all-around field-effect transistors and semiconductor quantum computing devices. In this paper, high-quality SiGe/Si multilayers have been grown by a reduced-pressure chemical vapor deposition system. The effects of temperature, pressure, interface processing (dichlorosilane (SiH2Cl2, DCS) and hydrogen chloride (HCl)) on improving the transition thickness of SiGe to Si interfaces were investigated. The interface quality was characterized by transmission electron microscopy/atomic force microscopy/high-resolution X-ray diffraction methods. It was observed that limiting the migration of Ge atoms in the interface was critical for optimizing a sharp interface, and the addition of DCS was found to decrease the interface transition thickness. The change of the interfacial transition layer is not significant in the short treatment time of HCl. When the processing time of HCl is increased, the internal interface is optimized to a certain extent but the corresponding film thickness is also reduced. This study provides technical support for the acquisition of an abrupt interface and will have a very favorable influence on the performance improvement of miniaturized devices in the future.

Ge0.92Sn0.08/Ge multi-quantum-well LEDs operated at 2-μm-wavelength on a 12-inch Si substrate

The development of an efficient group-IV light source that is compatible with the CMOS process remains a significant goal in Si-based photonics. Recently, the GeSn alloy has been identified as a promising candidate for realizing Si-based light sources. However, previous research suffered from a small wafer size, limiting the throughput and yield. To overcome this challenge, we report the successful growth of GeSn/Ge multiple-quantum-well (MQW) p-i-n LEDs on a 12-inch (300-mm) Si substrate. To the best of our knowledge, this represents the first report of semiconductor LEDs grown on such a large substrate. The MQW LED epitaxial layer is deposited on a 12-inch (300-mm) (001)-oriented intrinsic Si substrate using commercial reduced pressure chemical vapor deposition. To mitigate the detrimental effects of threading dislocation densities on luminescence, the GeSn/Ge is grown pseudomorphically. Owing to the high crystal quality and more directness in the bandgap, enhanced electroluminescence (EL) integrated intensity of 27.58 times is demonstrated compared to the Ge LED. The MQW LEDs exhibit EL emission near 2 μm over a wide operating temperature range of 300 to 450 K, indicating high-temperature stability. This work shows that GeSn/Ge MQW emitters are potential group-IV light sources for large-scale manufacturing.

Germanium wafers for strained quantum wells with low disorder

We grow strained Ge/SiGe heterostructures by reduced-pressure chemical vapor deposition on 100 mm Ge wafers. The use of Ge wafers as substrates for epitaxy enables high-quality Ge-rich SiGe strain-relaxed buffers with a threading dislocation density of (6±1)×105 cm−2, nearly an order of magnitude improvement compared to control strain-relaxed buffers on Si wafers. The associated reduction in short-range scattering allows for a drastic improvement of the disorder properties of the two-dimensional hole gas, measured in several Ge/SiGe heterostructure field-effect transistors. We measure an average low percolation density of (1.22±0.03)×1010 cm−2 and an average maximum mobility of (3.4±0.1)×106 cm2/Vs and quantum mobility of (8.4±0.5)×104 cm2/Vs when the hole density in the quantum well is saturated to (1.65±0.02)×1011 cm−2. We anticipate immediate application of these heterostructures for next-generation, higher-performance Ge spin-qubits, and their integration into larger quantum processors.

Three-Dimensional Self-Ordered Multilayered Ge Nanodots on SiGe

Three-dimensional (3D) self-ordered Ge nanodots in cyclic epitaxial growth of Ge/SiGe superlattice on Si0.4Ge0.6 virtual substrate (VS) were fabricated by reduced pressure chemical vapor deposition. The Ge nanodots were formed by Stranski-Krastanov mechanism. By the Ge/SiGe superlattice deposition, dot-on-dot alignment and 〈100〉 alignment were obtained toward the vertical and lateral direction, respectively. Facets and growth mechanism of Ge nanodots and key factors of alignment were studied. Two types of Ge nanodots were observed, diamond-like nanodots composed of {105} and dome-like nanodots composed of {113} and {519} or {15 3 23} facets. The Ge nanodots tend to grow directly above the nanodots of the previous period as these regions show a relatively higher tensile strain induced by the buried nanodots. Thus, this dot-on-dot alignment is sensitive to the SiGe spacer thickness, and it degrades when the SiGe spacer becomes thicker. The Ge content of the SiGe spacer ranging from 45 to 52% affects the lateral alignment and the size uniformity of Ge nanodots because of the strain balance between the superlattice and the VS. By maintaining the strain balance, ordering of the 3D aligned Ge nanodots can be improved.

Isothermal Heteroepitaxy of Ge1-x Sn x Structures for Electronic and Photonic Applications.

Epitaxy of semiconductor-based quantum well structures is a challenging task since it requires precise control of the deposition at the submonolayer scale. In the case of Ge1-x Sn x alloys, the growth is particularly demanding since the lattice strain and the process temperature greatly impact the composition of the epitaxial layers. In this paper, the realization of high-quality pseudomorphic Ge1-x Sn x layers with Sn content ranging from 6 at. % up to 15 at. % using isothermal processes in an industry-compatible reduced-pressure chemical vapor deposition reactor is presented. The epitaxy of Ge1-x Sn x layers has been optimized for a standard process offering a high Sn concentration at a large process window. By varying the N2 carrier gas flow, isothermal heterostructure designs suitable for quantum transport and spintronic devices are obtained.

Vertical alignment control of self-ordered multilayered Ge nanodots on SiGe

Self-ordered multilayered Ge nanodots with SiGe spacers on a Si0.4Ge0.6 virtual substrate are fabricated using reduced-pressure chemical vapor deposition, and the mechanism of vertical ordering is investigated. The process conditions of Ge and SiGe layer deposition are H2-GeH4 at 550 °C and H2-SiH4-GeH4 at 500 °C–550 °C, respectively. By depositing the SiGe at 550 °C or increasing Ge content, the SiGe surface becomes smooth, resulting in vertically aligned Ge nanodots to reduce strain energy. Ge nanodots prefer to grow on the nanodot where the SiGe is relatively tensile strained due to the buried Ge nanodot underneath. By depositing at 500 °C and lowering Ge content, checkerboard-like surface forms, and the following Ge nanodots grow at staggered positions to reduce surface energy. The Ge nanodots are laterally aligned along the elastically soft 〈100〉 direction without pre-structuring resulting from the strain distribution.

High Crystallinity Ge Growth on Si (111) and Si (110) by Using Reduced Pressure Chemical Vapor Deposition

A method for high quality epitaxial growth of Ge on Si (111) and Si (110) is investigated by reduced pressure chemical vapor deposition. Two step Ge epitaxy (low temperature Ge seed and high temperature main Ge growth) with several cycles of annealing by interrupting the Ge growth (cyclic annealing) is performed. In the case of Ge seed layer growth below 350 °C for (111) and 400 °C for (110) orientation, huge surface roughening due to too high dislocation density is observed after the following annealing step. For both crystal orientations, a high crystallinity Ge seed layer is realized by combination of 450 °C growth with 800 °C annealing. Once the high-quality Ge seed layer is deposited, high crystal quality Ge can be grown at 600 °C on the seed layer for both crystal orientations. For the 5 μm thick Ge layer deposited with the cyclic annealing process at 800 °C, a Si diffusion length of ∼400 nm from the interface, RMS roughness below 0.5 nm and threading dislocation density of 5 × 106 cm−2 are achieved for both (111) and (110) substrates.

Lateral Selective SiGe Growth for Local Dislocation-Free SiGe-on-Insulator Virtual Substrate Fabrication

Dislocation free local SiGe-on-insulator (SGOI) virtual substrate is fabricated using lateral selective SiGe growth by reduced pressure chemical vapor deposition. The lateral selective SiGe growth is performed around a ∼1.25 μm square Si (001) pillar in a cavity formed by HCl vapor phase etching of Si at 850 °C from side of SiO2/Si mesa structure on buried oxide. Smooth root mean square roughness of SiGe surface of 0.14 nm, which is determined by interface roughness between the sacrificially etched Si and the SiO2 cap, is obtained. Uniform Ge content of ∼40% in the laterally grown SiGe is observed. In the Si pillar, tensile strain of ∼0.65% is found which could be due to thermal expansion difference between SiO2 and Si. In the SiGe, tensile strain of ∼1.4% along 〈010〉 direction, which is higher compared to that along 〈110〉 direction, is observed. The tensile strain is induced from both [110] and [−110] directions. Threading dislocations in the SiGe are located only ∼400 nm from Si pillar and stacking faults are running towards 〈110〉 directions, resulting in the formation of a wide dislocation-free area in SiGe along 〈010〉 due to horizontal aspect ratio trapping.

Growth of 28Si Quantum Well Layers for Qubits by a Hybrid MBE/CVD Technique

Isotopically enriched 28Si quantum well layers in SiGe/Si/SiGe heterostructures are an excellent material platform for electron spin qubits. In this work, we report the fabrication of 28SiGe/28Si/28SiGe heterostructures for qubits by a hybrid molecular beam epitaxy (MBE) / chemical vapour deposition (CVD) growth, where the thick relaxed SiGe substrates are realised by a reduced-pressure CVD and the 28SiGe/28Si/28SiGe stacks are grown by MBE Here, we achieve a fully strained 28Si quantum well layer in such heterostructures with a 29Si concentration as low as 200 ppm within the MBE grown layers. It concludes that 29Si primarily originates from the residual natural Si vapour in the MBE chamber. A reliable surface preparation combining ex situ wet chemical cleaning and in situ annealing and atomic hydrogen irradiation offers epitaxy ready CVD grown SiGe substrates with low carbon and oxygen impurities. Furthermore, we also present our studies about the growth temperature effect on the misfit dislocation formation in this heterostructure. It shows that the misfit dislocation formation is significantly suppressed at a low MBE growth temperature, such as 350 °C.

High Quality Ge Growth on Si (111) and Si (110) by Using Reduced Pressure Chemical Vapor Deposition

Heteroepitaxial growth of Ge on Si has great interest for various optoelectronic applications such as Ge photodiodes(1). However 4.2% of lattice mismatch causes dislocation formation and island growth. High quality Ge(001) growth techniques are reported in ref.(2-4). Moreover, Ge(111) surface is also interesting because of higher carrier mobility(5). Furthermore, Ge(110) is preferred orientation of virtual substrates for epitaxial graphene growth(6). In the case of the Ge deposition on Si(111) and Si(110) substrates, it seems that the process conditions used for Ge growth on Si(001) are not suitable to realize high crystallinity and smooth surface (7). In this paper, we present a method of high quality and smooth Ge layer growth on Si(111) and Si(110), which is the same level as the Ge growth on Si(001).Epitaxial growth of Ge on Si(111) and Si(110) is carried out using a reduced pressure chemical vapor deposition system. After HF last clean, a wafer is baked at 1000°C and cooled down to 600°C in H2 and further to 300-550°C in N2 to form a hydrogen-free Si surface. Then a 100 nm thick Ge layer is deposited as a seed layer using GeH4 with N2 carrier gas. Afterward the wafer is heated up to 450-650°C in H2 and the main part of Ge is deposited using a H2-GeH4 gas mixture. For threading dislocation density (TDD) reduction, annealing at 800°C in H2 is performed for several times (cyclic annealing) by interrupting the Ge growth. Atomic-force microscopy (AFM) is used for surface roughness analysis. Scanning transmission electron microscopy (STEM) and X-ray diffraction (XRD) are used for structural characterization of the Ge layer. Secco defect etching combined with angle view scanning electron microscopy (SEM) or optical microscope is used for TDD evaluation.Figure 1(a,b) summarize the root mean square (RMS) roughness of Ge(111) and Ge(110) seed layers grown at 300-550°C before and after postannealing at 600-800°C. If the growth temperature is lower than 350°C for Ge(111) and 400°C for Ge(110), a significant increase of the surface roughness is observed after postannealing at 700°C and 800°C, respectively. For both crystal orientations, the lowest RMS roughness is observed by depositing at 450°C for as deposited and postannealed samples. The maintained RMS roughness even after postannealing at 800oC may be indicating good crystal quality even at as deposited condition.To confirm the influence of the growth temperature on the crystallinity, cross section TEM images of the Ge(111) and the Ge(110) seed layers deposited at 300°C and 450°C are shown in Fig. 2(a-d). In the case of Ge growth at 300°C (Fig. 2(a,b)), a very high density of stacking faults (SF) and high surface roughness are observed for both crystal orientations. In contrast, by depositing at 450°C (Fig. 2(c,d)), lower SF density in the Ge layer is observed compared to that at 300°C. By postannealing, an improvement of crystallinity is observed for the Ge seed layers deposited at 450°C. However, in the case of 300°C, the crystallinity cannot be improved by the postannealing, because a too high density of dislocations and SF may cause irregular Ge atom migration. As the result, surface roughening occurs.Figure 3(a,b) show AFM surface roughness images after 5 μm-thick Ge(111) and Ge(110) deposited with cyclic annealing at 800°C, respectively. Clear terraces of ~0.3 and ~0.2 nm, whose heights are close to those of Ge(111) bilayer and Ge(110) monolayer, are observed, respectively. RMS roughness of the Ge(111) and the Ge(110) are 0.51 and 0.35 nm, respectively. These RMS roughnesses are comparable to a level reported for Ge (001) in ref.(1).Figure 4 shows TDD of Ge(111) and Ge(110) surfaces as a function of the Ge thickness deposited with cyclic annealing on Si(111) and Si(110) substrates. For both orientations, TDD of ~4×108 cm-2 is obtained for 500 nm-thick samples. With increasing the Ge thickness, the TDD is reduced and levels below TDD of ~5×106 cm-2 are achieved for both Ge (111) and Ge(110) for 5 μm-thick Ge.These methods enable high quality virtual substrate fabrication not only for (001) surfaces but also for (111) and (110) orientation without a chemical mechanical polishing process. References Lischke et al. Nature Photonics15 (2021) 925Yamamoto et al. Solid-State Electron. 60 (2010) 2Yamamoto et al. Semicond. Sci. Technol. 33 (2018) 124007 M. Hartmann et al. J. Appl. Phys. 95 (2004) 5905 H. Lee et al. IEDM Tech. Digest (2009) 09-457J-H. Lee et al. Science 344 6181(2014) 286M. Hartmann et al. J. Cryst. Growth 310 (2008) 5287 Figure 1

Viewing SiGe Heterostructure for Qubits with Dislocation Theory

SiGe/Si/SiGe heterostructure serves as one of the ideal semiconductor material system to build large scale electron spin qubits[1]. To further push the scalability and extend the coherence times of qubits built on SiGe/Si/SiGe heterostructures, there are several factors to improve, one of that is the lattice homogeneity of strained Si. One source of lattice homogeneity break down are dislocations. Due to the difficulties of high quality SiGe bulk crystal growth [2-3], relaxed SiGe is commonly grown on Si substrates by epitaxy. Viewing the SiGe/Si/SiGe heterostructure on native Si substrate, dislocations half loops form unavoidably because of the misfit between SiGe and the Si substrate. These dislocation half loops consist of threading segments extending through the whole heterostructure (figure 1 (a) and (c)) [4]. Due to the stress caused by the strained Si quantum well layer, the threading dislocations can be driven to glide, resulting in additional misfit segments in the lower interface of strained Si layer when the critical thickness is exceeded (figure 1 (b)) [5]. The extension of these misfit segments is blocked when they meet other perpendicular dislocations (figure 1 (d)) [6]. These misfit dislocations destroy strain uniformity and cause tilt inside the Si layer, resulting in a distortion of the valley splitting and ultimately, reducing the coherence time of qubits [7-8].In this work, we present the observation of dislocations in SiGe/Si/SiGe heterostructures for qubit application by plan-view TEM (Figure 1 (right)). Here, the experimental observations agree with dislocation theory that threading dislocations (some are marked by (b)) will glide and elongate to have misfit segments (some are marked by (c)) in the interface when two requirements are fulfilled: misfit exists between epitaxial layer and substrate; critical thickness is exceeded. When the misfit dislocations meet perpendicular misfit dislocation line, they are blocked since the thickness is not enough to glide over it [6]. This is the case in figure 1 right marked by (d). Due to the misfit segment generation and blocking effects, the misfit dislocation spacing is proportional to the threading dislocation density both theoretically and experimentally. These misfit dislocations bring local strain field around them [9], which disturb the desired homogeneous strain field by misfit. Therefore, misfit dislocation generation needs to be suppressed if one wants to achieve homogeneous strain in Si thin layer in large scale.According to Matthews-Blakeslee theory, one can avoid the formation of misfit dislocations in the Si interface by controlling the strained layer within the critical thickness. The critical thickness of Si on Si0.7Ge0.3 is calculated as 8.5 nm. The Electron channeling contrast images of Si with difference thickness 10 nm and 5 nm grown on high threading dislocation relaxed Si0.7Ge0.3 buffer at 700°C by reduced pressure chemical vapor deposition in Figure 2 are collaborating with theory: obviously misfit dislocation appear in 10 nm Si on relaxed Si0.7Ge0.3 (Figure 2 (left)) and no misfit dislocation are presented in 5 nm Si on Si0.7Ge0.3 (Figure 2 (right)).Our results show that dislocation generation and movement needs to be taken into consideration to further develop SiGe heterostructure based qubits.

Investigation of Arsenic Transient Enhanced Diffusion From Emitter Process at 550 °C Si:As RP-CVD Epitaxy Using Disilane Precursor

Reduced Pressure Chemical Vapor Deposition (RP-CVD) Epitaxy bellow 600 °C is studied for 3D sequential integration [1] where cyclic deposition is needed. Another approach can be useful with Si epitaxy at temperature bellow 600 °C : the deposition of amorphous Si on dielectric during non-selective epitaxy combined with solid phase epitaxy regrowth (SPER) to extend the monocrystalline area. Indeed, using temperature above 600 °C during non-selective epitaxy, a polycrystalline Si film is formed on dielectric. This technique has been used in heterojunction bipolar transistor for the non-selective base deposition [2] and can also be used to ensure a fully monocrystalline emitter.Si:As process has been developed at 550 °C using disilane (Si2H6) as Si precursor and Arsine (AsH3) for As precursor. At this temperature, disilane is mandatory to ensure a sufficient growth rate. The disilane process will be compared to a process of reference, using silane (SiH4) precursor at 620 °C. The As dopant concentration targeted is between 1x20 at.cm-3 and 5x20 at.cm-3. Finally, the dopant diffusion is controlled on non-productive Si(100) wafer (NPW), without pattern, by SIMS for both processes before and after thermal budget (720 °C, 1 h + high temperature Spike anneal) to simulate the thermal budget undergone by the emitter.Thanks to the ASTAR system [3] from NanoMEGAS, the crystal orientation and phase maps of the emitter are extracted for both processes (Fig 1.a). ASTAR system is based on the Automated Crystal Orientation Mappings technique used on a Transmission Electron Microscope (ACOM-TEM). With silane precursor, a poly-emitter is generated whereas the emitter is fully monocrystalline with disilane. The amorphous deposition coupled with SPER ensure a fully monocrystalline emitter. SIMS analysis have been performed and show abnormal diffusion of As with disilane process. To understand the causes of the diffusion, both Si:As processes have been reproduced on NPW by full sheet epitaxy. The abnormal diffusion is still observed with the disilane process (Fig 1.b). Compared to diffusion length extracted from [4] (19nm) the diffusion of As is enhanced. Moreover, As enhanced diffusion occurs for low temperature thermal budget (Fig. 1.c).Historically, defects generated from implantation are known to enhance the diffusion length of the dopant. This phenomenon is called Transient Enhanced Diffusion (TED) and it has been studied and observed from dopant implantation [5]. The implantations generate a supersaturation of interstitials defects (such as auto-interstitial) which enhance the dopant diffusion for low temperature thermal budgets. This is a transient effect because the enhanced diffusion occurs in a short time [5]. In our case, several anneal at 720 °C were applied on the disilane Si:As layer from 1 h to 24 h (Fig. 1.d). Most of the diffusion occurs after the annealing at 720 °C, 1 h. These results highlight the transient effect of the As diffusion using disilane process. With the disilane process, TED of As occurs. Indeed, enhanced diffusion of Arsenic appears only for low temperature annealing and the effect is also transient. Compared to implantation which generates defects during the bombardment, low temperature epitaxy generates defects when the growth rate is too high. The molecules from the gas phase are adsorbed on the surface and break down on atoms (called adatom). The adatoms diffuse on the surface to find a suitable site. During low temperature epitaxy, when the growth rate is too high, the adatom don’t have enough time to diffuse on a suitable site and generate defects.Finally, dopant profile analysis will be completed by atomic force microscopy (AFM) and sheet resistance measurement. The AFM will provide an evolution of the surface topography with the annealing. The sheet resistance, coupling with SIMS, will help to extract the deactivation of dopant. The causes of the TED from disilane process at 550 °C will be discussed and experimental results will be provided.[1] L. Brunet et al., IEEE International Electron Devices Meeting (IEDM), 2018[2] Holger Rücker and Bernd Heinemann, Semicond. Sci. Technology, 2018[3] A. Valery, Doctoral dissertation. Université Grenoble Alpes, 2017[4] S. W. Jones, "Diffusion in silicon". IC Knowledge LLC, 2008[5] S. C. Jain, et al., Journal of applied physics, 2002 Figure 1