Output Current Ripple Reduction Research Articles

Research on Cascaded On‐Board DC/DC Converter Based on Three‐Phase Interleaved LLC

ABSTRACTThe on‐board DC/DC converter proposed in this research consists of a Buck converter and a three‐phase interleaved LLC resonant converter. This paper analyzes the average current and output current ripple characteristics of the rear‐stage converter in addition to explaining the topology and working principles of the front‐stage Buck converter and the rear‐stage three‐phase interleaved LLC resonant converter. To establish a single‐phase fundamental equivalent circuit for the rear‐stage converter, apply the fundamental wave analysis method, and it is essential for comprehending the impact of relevant system parameters on voltage gain characteristics and resonant operating regions. Conducting research on the two‐stage on‐board DC/DC converter's control strategy involves establishing small‐signal circuit models for both front and rear stage converters, derivation of parameters for double closed‐loop control, and determination of the control strategy employing phase‐shifted current sharing for the rear‐stage converter in cases where significant tolerance exists in resonant components. The simulation for a two‐stage on‐board DC/DC converter results indicates that under various conditions of resonant component tolerance, the converter is capable of achieving balanced phase currents and demonstrates minimal output current ripple prior to capacitor filtering. A 1.5‐kW experimental prototype has been fabricated, and the experimental findings indicate that the output voltage remains stable at 13.8 V despite fluctuations in input voltage. The highest efficiency of the prototype is about 96.27%, and the utilization of phase‐shifting current balancing control results in a notable reduction in output current ripple. This provides more evidence that the design of a two‐stage on‐board DC/DC converter is correct.

Analysis of the effect of mutual inductance on reducing output current ripple of the modified DC-DC Cuk converter

DC-DC converters exhibiting minimal input and output ripple are extensively employed across a diverse range of applications. This paper presents a proposed modification to the DC-DC Cuk converter. The converter is developed by modifying a conventional Cuk DC-DC converter to exhibit boost characteristics. The DC-DC converters possess the capability to function as versatile units that can be employed in a multitude of applications, ranging from DC-DC conversion to DC-AC conversion (inversion). This paper presents a novel DC-DC converter design that aims to achieve reduced ripple in both input and output currents. By employing the principle of mutual inductance, it is possible to further mitigate the presence of ripple current. The analysis of the impact of mutual inductance on the output voltage and ripple current of the proposed converter has been conducted. The validity of the derived analytical method has been confirmed through both simulated and experimental investigations. The utilization of mutual inductance in the proposed modified Cuk converter has been demonstrated to result in reduced current ripple.

A Soft-Switched Three-Phase Inductor Coupling Quasi-Z-Source Integrated Charger with Reduced Output Current Ripple for Electric Vehicles

A Soft-Switched Three-Phase Inductor Coupling Quasi-Z-Source Integrated Charger with Reduced Output Current Ripple for Electric Vehicles

Output Current Ripple and Efficiency Optimal Control Method for Multi-Phase Interleaved LLC Resonant Converter

The interleaving technique is required for LLC resonant converters to achieve high power levels, handle higher input/output currents, and reduce output current ripple. However, the high system efficiency and the low output current ripple for the multi-phase LLC resonant converter cannot be achieved at the same time at low and medium power levels. Most methods try to keep the multi-phase LLC resonant converter in load-sharing mode regardless of the power level, which will result in low system efficiency at low and medium power levels. In this paper, an output current ripple and efficiency optimal control method with finite load distribution schemes is proposed for the multi-phase LLC resonant converter to balance the efficiency and output current ripple. The optimal control method improves the efficiency as much as possible while keeping output current ripple low. According to the calculation of output current ripple and efficiency, the optimal load distribution scheme is selected. The pulse-frequency modulation (PFM) and phase-shift modulation (PSM) hybrid control is applied to regulate the load of each phase. An analysis is provided, and a 540-W three-phase interleaved LLC resonant converter is built to verify the superiority.

Optimal Current Ripple PWM for Three-Level Inverter With Common Mode Voltage Reduction

Three-level inverter has been widely used in electric drives and renewable power generation system. However, the common mode voltage (CMV) and output current ripple reduction of three-level inverter should be carefully regulated for the appropriate operation. As these two targets are mutually interrelated, the conventional space vector modulation (SVM) scheme cannot cope with them decently. To overcome this drawback, this paper proposes a novel modified SVM scheme to realize CMV and current ripple reduction simultaneously. The generating mechanism of output current ripple is analyzed, and the relationship between current ripple and utilized vectors is quantitatively described. Based on the analyses, the proposed optimal current ripple and CMV reduction pulse width modulation (OCR-CMVRPWM) method adopts four voltage vectors (large, medium, small and zero vectors) to reduce root mean square (RMS) value of current ripple by allocating the sequence and dwell times of utilized vectors. Compared to the existing PWM methods, the proposed OCR-CMVRPWM scheme can reduce the peak of CMV to half of value using the conventional SVM, and obtain a significant reduction of output current total harmonic distortion (THD). The effectiveness of the proposed method is validated by both simulation and experimental results.

Current-Sharing Worst-Case Analysis of Three-Phase CLLC Resonant Converters

Three-phase CLLC resonant converters provide higher power conversion capability compared to half-bridge and full-bridge structures. In addition to the unique features of CLLC converters for bi-directional applications, the three-phase structure provides significantly reduced output current ripple (smaller output capacitor), parallel power processing (reduced components size and current peak stress), and better thermal distribution (smaller heatsinks). However, with practical, i.e. non-zero, resonant component tolerances, these benefits are normally less, and sometimes significantly less than expected in the ideal case. In this paper, the unbalanced behavior of the converter with fifteen unknown resonant components is identified and analyzed. A new analysis methodology is proposed to investigate the worst-cases of current-sharing among above 32000 possible scenarios in three-phase CLLC resonant converters. In addition, the paper shows that phase-shifting techniques can be effective to mitigate the unbalanced behavior of the converter. The proposed analysis in this paper helps to determine the highest admissible tolerance in the components to keep the converter working within a certain range of unbalanced behavior without requiring any balancing techniques. The proposed analytical framework is verified with experimental and simulation results of a 3-kW bidirectional three-phase CLLC experimental prototype.

Hybrid Dual-Loop Control for Current Regulation and Low-Frequency Ripple Rejection in Led Drivers

This paper presents a new hybrid dual-loop control system for the DC/DC LLC resonant converter, operating as a downstream DC/DC converter in a two independent stage offline LED driver. The outer loop employs a PI controller to maintain the average LED current regulated at the reference value and reject parametric variation. The inner loop implements an adaptive periodic disturbance rejection (APDR) subsystem, thus conceiving the hybrid PI\&APDR controller. The APDR subsystem is designed to strictly reject the bus voltage ripple and limit its transmission to the LED current. Experimental results show the proposed controller feasibility in achieving good tracking behavior, reduced output current ripple under different bus voltage ripple amplitude and frequency, robustness against parametric variations, and simple implementation and design. For the sake of completeness, the proposed PI&APDR is compared with the conventional proportional resonant controller employing experimental results and extra analysis based on simulations.

AC–DC Flyback Dimmable LED Driver with Low-Frequency Current Ripple Reduced and Power Dissipation in BJT Linearly Proportional to LED Current

In this paper, a dimmable light-emitting diode (LED) driver, along with the low-frequency current ripple decreased and the bipolar junction transistor (BJT) power dissipation reduced, is developed. This driver is designed based on a single-stage flyback converter. On the one hand, the low-frequency output current ripple reduction is based on the physical behavior of the linear current regulator. On the other hand, when the voltage across the LED string is decreased/increased due to dimming or temperature, the output voltage of the flyback converter will be automatically regulated down/up, thereby making the power dissipation in the BJT linearly proportional to the LED current. By doing so, not only the power loss in the linear current regulator will be decreased as the LED current is decreased or the LED temperature rises, but also the output current ripple can be reduced. Furthermore, the corresponding power factor (PF) is almost not changed, and the total harmonic distortion (THD) is improved slightly. In addition, the LED dimming is based on voltage division. Eventually, a 30 W LED driver, with an input voltage range from 85 to 295 Vrms and with 24 LEDs in series used as a load, is developed, and accordingly, the feasibility of the proposed LED driver is validated by experimental results.

Analysis and Design of Coupled Inductor for Interleaved Buck-Type Voltage Balancer in Bipolar DC Microgrid

A voltage balancer (VB) can be used to balance voltages under load unbalance in either a bipolar DC microgrid or LVDC (Low voltage DC) distribution system. An interleaved buck-type VB has advantages over other voltage balance topologies for reduction in output current ripple by an aspect of configuration of a physically symmetrical structure. Similarly, magnetic coupling such as winding two or more magnetic components into a single magnetic component can be selected to enhance the power density and dynamic response. In order to achieve these advantages in a VB, this paper proposes a VB with a coupled inductor (CI) as a substitute for inductors in a two-stage interleaved buck-type VB circuit. Based on patterns of switch poles under load variation, the variation in inductor currents under four switching patterns is induced. The proposed CI is derived from self-inductance based on the configuration structure that has a two-stage interleaved buck type and mathematical design results based on the coupling coefficient, where the coupling coefficient is a key factor in the determination of the dynamic response of the proposed VB in load variation. According to the results, a prototype scale is implemented to confirm the feasibility and effectiveness of the proposed VB.

Output current ripple reduction of LED driver using ceramic‐capacitor‐input circuit and buck‐boost converter

AbstractThis article proposes an LED driver that consists of a ceramic‐capacitor‐input rectifier and a buck‐boost converter. The LED driver has an advantage of long life because it does not contain any electrolytic capacitors. However, the issue with electrolytic capacitor‐less LED driver is that the ripple of the smoothed voltage becomes large due to insufficient capacitance of the smoothing capacitor. The proposed method, which uses the discontinuous current mode of a buck‐boost converter, reduces the output current ripple under such conditions. Experimental results using a 5.7 W LED driver prototype demonstrate that the proposed method reduces the output current ripple and that the percent flicker becomes 4.4%, which is smaller than the recommended upper limit of 8%.

Output Current Ripple Reduction of LED Driver Using Ceramic-Capacitor-Input Circuit and Buck-Boost Converter

Output Current Ripple Reduction of LED Driver Using Ceramic-Capacitor-Input Circuit and Buck-Boost Converter

Unbalanced Three-Phase <inline-formula> <tex-math notation="LaTeX">$LLC$</tex-math> </inline-formula> Resonant Converters: Analysis and Trigonometric Current Balancing

Three-phase $LLC$ resonant converters can handle very high power levels beyond the capabilities of half-bridge and full-bridge $LLC$ topologies. Among other characteristics, three-phase $LLC$ structures reduce output current ripple (small output filter), enable parallel power processing (low peak current), and provide good thermal distribution. However, all these key advantages can be severely compromised due to passive components tolerances, leading to undesired current balance issues in three-phase $LLC$ resonant converters. Tolerances in resonant tank passive components are inevitable and lead to unequal peak currents between phases, uneven temperature distribution, and large output current ripple. This paper investigates the imbalances in three-phase $LLC$ converters and proposes a novel trigonometric current balancing (TCB) technique using phasor analysis. In this strategy, the required input voltage phase angles are calculated to achieve balanced phase currents, even under severe unbalanced conditions. In some cases, the output filter current ripple is reduced to less than half. The methodology is verified with a 3-kW experimental prototype, which validates the analytical framework and effectiveness of TCB.

Literature Survey of Interleaved DC-DC Step-Down Converters for Proton Exchange Membrane Electrolyzer Applications

Recently, the use of electrolyzers for hydrogen production through water electrolysis is of great interest in the industrial field to replace current hydrogen production pathways based on fossil fuels (e.g. oil, coal). The electrolyzers must be supplied with a very low DC voltage in order to produce hydrogen from the deionized water. For this reason, DC-DC step-down converters are generally used. However, these topologies present several drawbacks from output current ripple and voltage gain point of view. In order to meet these expectations, interleaved DC-DC step-down converters are considered as promising and interesting candidates to supply proton exchange membrane (PEM) electrolyzers. Indeed, these converters offer some advantages including output current ripple reduction and reliability in case of power switch failures. In addition, over the last decade, many improvements have been brought to these topologies with the aim to enhance their conversion gain. Hence, the main goal of this paper is to carry out a thorough state-of-the-art of different interleaved step-down DC-DC topologies featuring a high voltage gain, needed for PEM electrolyzer applications.

Optimal space vector pulse width modulation strategy of neutral point clamped three‐level inverter for output current ripple reduction

Based on the analysis of the space vector modulation strategies for three-level inverters, the duration assignment of the two redundant switching states and the selection of different switching sequences can be considered as two degrees of freedom. The impacts of these two degrees of freedom on the quality of output current are evaluated by using the mathematical model of current ripple established in this study. Moreover, according to the principle of minimum rms value of output current ripple, the optimal assignment of the two redundant states and the optimal distribution of switching sequences are determined. Thus, the optimisation of the output current waveform is realised. The simulation and experimental results show that, for the proposed strategy, the total harmonic distortion (THD) of output current and the weighted THD of output voltage are both lower than that of the conventional strategies.

Coupled-Inductor-Based High-Step-Down-Ratio Converter with Output Current Ripple Reduction

Even though the coupled-inductor-based high-step-down-ratio converters can achieve a higher step-down voltage gain than the traditional buck converter, their output current suffer from a high output current ripple, causing a high output voltage ripple. Therefore, a bulky electrolytic output capacitor is usually used to suppress the output voltage ripple. Moreover, the longevity of the output electrolytic capacitor is highly dependent on the output current ripple. In [6–8], a passive current ripple cancellation circuit was applied to the DC–DC converters to reduce the output current ripple. However, these literatures did not mention and analyze the situations for coupled-inductor converters. Moreover, the same concept, including analysis and design, cannot be directly applied to the coupled-inductor-based converters. Therefore, in this paper, the analysis, design, and experimental results of the current ripple cancellation circuit applied to the coupled-inductor-based high-step-down-ratio converter are given to verify the effectiveness.

Discontinuous Space Vector PWM Strategy of Neutral-Point-Clamped Three-Level Inverters for Output Current Ripple Reduction

In order to meet the high performance and efficiency requirements, a new space vector-based discontinuous modulation strategy for neutral-point clamped three-level inverter is presented in this paper. Different from the conventional discontinuous PWM (DPWM) strategies, a new clamping state is applied to synthesize the reference voltage under the condition of low modulation index. The rms value of output current ripple for different clamping states are calculated, and then the distribution of the new clamping state and the other two clamping states adopted in conventional DPWMs is optimized based on the calculation results. The switching sequences are redesigned according to the new distribution of the three clamping states. The output voltage and current, switching loss, neutral-point voltage ripple and the common mode voltage of the proposed DPWM strategy and DPWM0–DPWM3 are compared by simulation and experimental results. The results show that by the use of the proposed strategy, the values of total demand distortion of output current ( I TDD) and weighted total harmonic distortion of output voltage $({\boldsymbol{V}_{{\mathbf{WTHD}}}})$ are the lowest. Furthermore, the product of switching loss and $I_{\rm TDD}$ of the proposed strategy maintains the lowest within a large range of modulation index-load angle plane. It can be concluded that the utilization of the new clamping state and optimal distribution of different clamping states could enhance the output performance of the inverter. Moreover, the high-efficiency requirement can also be realized at the same time.

Eliminated common-mode voltage pulsewidth modulation to reduce output current ripple for multilevel inverters

The paper presents an analysis on the output current ripple in zero common-mode voltage (ZCMV) PWM control of multilevel inverters. The modulation strategy for common-mode voltage (CMV) elimination in multilevel inverters is based on the “three zero common-mode vectors” principle. The space vector diagram, which consists of vectors of ZCMV, is fully explored by properly depicting the base voltage vectors and their corresponding active switching vectors. The switching patterns are limited to those of three switching states each of which is symmetrically distributed. Based on the PWM process simplified to that of a two-level inverter with three allowable switching states and the degree of freedom existing in the switching states arrangement, a novel carrier-based pulsewidth-modulated (PWM) method with optimized output current ripple is proposed. Compared to the existing PWM methods which utilize the same kind of switching patterns, the proposed PWM method has reduced considerably the rms current ripple and total harmonic distortion (THD) of the output current in a wide region of the modulation index. The effectiveness of the proposed method is validated by both simulation and experimental results.

Interleaved DC-DC Converter with Discrete Duty Cycle and Open Loop Control

Abstract The authors present the control principle of the multiphase interleaved DC-DC converter that can be used to vastly reduce output current ripple of the converter. The control algorithm can be easily implemented by using microcontroller without current loop in each phase. The converter works in discontinuous conduction mode (DCM) but close to boundary conduction mode (BCM). The DC-DC converter with such a control algorithm is useful in applications that do not require precise current adjustment. The prototype of the converter has been built. The experimental results of the current ripple are presented in the paper.

Two‐transformer‐based full‐bridge soft‐switching DC–DC converter with improved characteristics

A novel two-transformer-based full-bridge soft-switching DC–DC converter is proposed. The primary-windings of the two transformers are connected in series, while the two secondary windings of the two transformers are connected to the output through a semi-active full-bridge rectifier and a passive full-bridge rectifier, respectively, in parallel. The voltage stress on the primary windings of the transformers is reduced, as well as the current stresses of the secondary windings of the transformers and the rectifying devices. Zero-voltage-switching is realised for the MOSFETs, while zero-current switching is achieved for all the diodes by adopting the secondary side phase-shift control. In comparison with existing topologies, the turn-off current and loss of the secondary side MOSFETs are reduced, because only half of the output current flows through these switches. The circulating current is effectively suppressed, which leads to less conduction loss. The proposed converter also offers some advantages, such as smaller value and size of high-frequency-link inductor and reduced output current ripple. The converter can operate in the buck and boost modes to fulfil the application demands with wide input/output voltage ranges. The operating principle of the proposed converter is analysed in detail and verified with experimental results.

Digitally Controlled 4-Phase Bi-Directional Interleaved Dc-Dc Converter with Coupled Inductors / Digitāli Vadāms 4 Fāžu Divvirziena Līdzstrāvas Pārveidotājs Ar Saistītajām Droselēm

Abstract The main advantages of multiphase interleaved DC-DC converters over single-phase converters are reduced current stress and reduced output current ripple. Nevertheless, inductor current ripple cannot be reduced only by an interleaving method. The integrated magnetic structure can be used to solve this problem. In this paper, the application of 2-phase coupled inductor designed in a convenient way by using commercially manufactured coil formers and ferrite cores is analysed to develop a 4-phase interleaved DC-DC converter. The steady state phase and output current ripple in a boost mode of the interleaved bidirectional DC-DC converter with integrated magnetics are analysed. The prototype of the converter has been built. The experimental results of the current ripple are presented in the paper.