Wirelength Reduction Research Articles

Learning placement order for constructive floorplanning

Floorplanning is an early and essential task of physical design. Recently, there has been a surge in the application of learning-based methods to tackle floorplanning problem. A prevalent approach involves training a reinforcement learning (RL) agent to sequentially place blocks on a chip canvas. However, existing methods mainly focus on learning block placement, relying on heuristic rules for placement order determination. In contrast to previous approaches, we propose an RL-based method to determine the placement order. Based on block features and states, an agent is trained to select the block for placement. Once a block is selected, we enumerate all potential relative positions captured by sequence pairs and select the optimal placement. After establishing the layout topology, we further optimize wirelength through linear programming. Experimental results demonstrate the effectiveness of our proposed method. On the original-outline MCNC benchmarks, our method achieves a notable 25.2% average improvement in wirelength compared to a recent learning-based method. Additionally, when applied to rescaled-outline benchmarks from MCNC and GSRC, our method outperforms state-of-the-art results, resulting in an average wirelength reduction of 12.5%.

Automatic device arrangement and wiring for fire alarm systems in metro stations: A case study

Fire alarm systems in metro stations play an important role in safeguarding lives and properties. The design process for these systems is complex and time-consuming due to the diversity of device types, wide distribution of device locations, and numerous compulsory design codes. This paper proposes an automatic design framework for fire alarm systems aimed at enhancing design efficiency. The framework includes five automated processes: information preprocessing, device arrangement, system loop generation, device wiring, and result generation. By converting the computer-aided design (CAD) results into building information models (BIM), building information and related professional device information are obtained, addressing the need for fire alarm system (FAS) design to integrate with multiple disciplines. The process can also automatically arrange FAS devices according to design specifications. Optimization algorithms, such as Ant Colony Algorithm and Prim Algorithm, are used to determine the device connection order and solve the problems of obstacle avoidance and orthogonal connections between two points. Compared to traditional design methods, the proposed automatic design framework for fire alarm systems in metro stations can not only satisfy the mandatory design requirements but also avoid the cumbersome and repetitive design process, providing new solutions for designers. Additionally, it can reduce wire length and save on construction costs. Using a real metro station as a case study, it is calculated that the automatic design can save between 8 % and 48 % of the wire length.

A multi‐tap‐receiver based wireless power transfer system with multiple independent outputs and reduced wire length

A multi‐tap‐receiver based wireless power transfer system with multiple independent outputs and reduced wire length

An efficient 3D IC partitioning approach using satin bowerbird optimization for reduced TSV count and improved heat dissipation

Net list partitioning achieves paramount importance in the physical architecture design step of Three Dimensional (3D) Very Large Scale Integrated (VLSI) circuits. The performance of all subsequent steps like floor layout, placement, pin assignment, and routing in the physical architecture design of the VLSI circuit are heavily affected by the outcomes of partitioning steps. Wire length between gates is reduced by 3D Integrated Circuit (IC) due to compact footprint as well as vertical inter connections among dies. This reduced wire length in turns responsible for less energy consumption and reduced connection delays. In this paper, Satin Bowerbird Optimization (SBO) is applied to solve 3D IC partitioning challenges. The suggested 3D IC partitioning technique is aimed at reducing the number of Through Silicon Vias (TSV) and measurements have also been taken to reduce heat dissipation. The presence of a significant amount of TSVs expands the chip area. 3D ICs have considerably greater densities of power because of advances in the technology and a vastly increased variety of components with high frequency. The heat generated by the used power has an impact on the performance and dependability of the chip. In this experiment, SBO is used as a multi-objective optimization method to achieve two objectives simultaneously - TSV count minimization and heat dissipation reduction. The performance of the suggested SBO - based approach is assessed utilizing the Giga Scale Research Center (GSRC) benchmark circuits. The applicability of the suggested technique is judged by comparing the outcomes with thermal-aware multilevel hyper-graph partitioning method. The findings of the comparison reveal that the suggested technique outperforms the thermal-aware multilevel hyper-graph partitioning approach by lowering the number of TSV count, maximum area requirement, and power density by 16.99%, 9.94% and 29.10% respectively. The performance of the experiment is also compared with existing Simulated Annealing and Tabu search based techniques. In both cases, the proposed method achieves better result by lowering TSV by 26.03% and 27.31%, and reducing area by 6.59% and 6.59%, respectively.

Multi-objective Floorplanning optimization engaging dynamic programming for system on chip

The quest for optimal VLSI Floorplanning (FP) addressing noteworthy challenges namely Area, Wirelength, and Temperature remains an ongoing field of research. Prevailing FP designs individually optimize these constraints that increase the model complexity with reduced efficiency. Given this motivation, this study provides an optimum FP aimed at minimizing the overall chip area by adhering to the standard design requirements. Accordingly, the divide-and-conquer model of Dynamic Programming (DP) adopted in this work simultaneously optimizes the chip area by devising separate analytical cost functions related to the physical design parameters that are then collated to yield the compact Floor plan. The formulated DP optimization coined as Weighted Aggregated DP-Based FP (WADPFP) adaptively tunes the cost function using rank-sum scaled weights and the discount factor thereby reducing congestion and hotspots. This objective is met using two novel recursive functions ensuring temperature and area scalability. Simulation and synthesis of the proposed FP on the Microelectronic Centre of North Carolina (MCNC) and Gigascale Systems Research Center (GSRC) Benchmark circuits demonstrated the viability of the automated FP design by registering 6.05%, 13%, and 4.35% reduction in area, wirelength, and temperature respectively in comparison with the traditional and recent peers. Additional analysis on the AMI49_X benchmark circuits emphasizes the scalable nature of the introduced WADPFP.

A comprehensive investigation of a solar array with wire length under partial shading conditions

ABSTRACT Partial shading condition (PSC) leads to mismatch losses and multiple peaks on the output curves. Several static-based reconfigurations like total cross-tied (TCT), skyscraper reconfiguration (SSR), and odd-even reconfiguration (OER) were reported to address these issues. But, less shade dispersion and more wiring losses occur in these arrays. This work focuses on both power improvement and wire length reduction of solar arrays under PSC. Based on the reduced wire length to more than 50% for SSR over OER, a novel enhanced skyscraper reconfiguration (ESR) is proposed in this work. ESR is cheaper by 169.13 INR and 1699.07 INR as compared to SSR and OER respectively. Further, the performance of the novel ESR is compared by obtaining several parameters like fill factor (FF), efficiency (Ƞ), global power (GP), execution ratio (ER), current loss (IL), and mismatch loss (ML) with the existing SSR and OER. It is observed that the Ƞ is improved by 4% and 13.05% and GP is maximized by 3.74W and 4.48W for the novel-proposed ESR over SSR and OER, which is experimentally verified under regional and corner shadings respectively. Overall, the novel-proposed ESR confirms its supremacy over other considered models in this study.

Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop Stacking

Circuits that are placed with very low (or high) aspect ratio are susceptible to routing overflows. Such designs are difficult to close and usually end up with larger area with low area utilization. In this article, we propose two routability optimization methods to implement designs even with very low (or high) aspect ratio and high area utilization. First, we find the best assignment of non-uniform placement utilization through convolutional neural network model, and cell placement is performed while respecting the placement utilization. This allows many cells to be spread out over the entire design rather than being centered. The experiments show that most overflows of 16.5% occurring in cell placement are removed with 23.1% reduction in wire length; this is the result of further improving overflow of 9.8% compared to a conventional method. In the second, some flip-flops are selectively stacked to reduce the routing resources used for clock routing. U-Net model is built with graph attention network to predict the congestion after clock-tree synthesis, and the flip-flops in highly congested areas are selected for stacking. The proposed method improves the overflows, which occurs after clock-tree synthesis, by 22.1%.

An Enhanced Deep Reinforcement Learning-Based Global Router for VLSI Design

Global routing is a crucial step in the design of Very Large-Scale Integration (VLSI) circuits. However, most of the existing methods are heuristic algorithms, which cannot conjointly optimize the subproblems of global routing, resulting in congestion and overflow. In response to this challenge, an enhanced Deep Reinforcement Learning- (DRL-) based global router has been proposed, which comprises the following effective strategies. First, to avoid the overestimation problem generated by Q -learning, the proposed global router adopts the Double Deep Q -Network (DDQN) model. The DDQN-based global router has better performance in wire length optimization and convergence. Second, to avoid the agent from learning redundant information, an action elimination method is added to the action selection part, which significantly enhances the convergence performance of the training process. Third, to avoid the unfair allocation problem of routing resources in serial training, concurrent training is proposed to enhance the routability. Fourth, to reduce wire length and disperse routing resources, a new reward function is proposed to guide the agent to learn better routing solutions regarding wire length and congestion standard deviation. Experimental results demonstrate that the proposed algorithm outperforms others in several important performance metrics, including wire length, convergence performance, routability, and congestion standard deviation. In conclusion, the proposed enhanced DRL-based global router is a promising approach for solving the global routing problem in VLSI design, which can achieve superior performance compared to the heuristic method and DRL-based global router.

GraphPlanner: Floorplanning with Graph Neural Network

Chip floorplanning has long been a critical task with high computation complexity in the physical implementation of VLSI chips. Its key objective is to determine the initial locations of large chip modules with minimized wirelength while adhering to the density constraint, which in essence is a process of constructing an optimized mapping from circuit connectivity to physical locations. Proven to be an NP-hard problem, chip floorplanning is difficult to be solved efficiently using algorithmic approaches. This article presents GraphPlanner, a variational graph-convolutional-network-based deep learning technique for chip floorplanning. GraphPlanner is able to learn an optimized and generalized mapping between circuit connectivity and physical wirelength and produce a chip floorplan using efficient model inference. GraphPlanner is further equipped with an efficient clustering method, a unification of hyperedge coarsening with graph spectral clustering, to partition a large-scale netlist into high-quality clusters with minimized inter-cluster weighted connectivity. GraphPlanner has been integrated with two state-of-the-art mixed-size placers. Experimental studies using both academic benchmarks and industrial designs demonstrate that compared to state-of-the-art mixed-size placers alone, GraphPlanner improves placement runtime by 25% with 4% wirelength reduction on average.

An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts

Managing the timing constraints has become an important factor in the physical design of multiple supply voltage (MSV) integrated circuits (IC). Clock distribution and module scheduling are some of the conventional methods used to satisfy the timing constraints of a chip. In this paper, we propose a simulated annealing-based MSV floorplanning methodology for the design of ICs within the timing budget. Additionally, we propose a modified SKB tree representation for floorplanning the modules in the design. Our algorithm finds the optimal dimensions and position of the clocked modules in the design to reduce the wirelength and satisfy the timing constraints. The proposed algorithm is implemented in IWLS 2005 benchmark circuits and considers power, wirelength, and timing as the optimization parameters. Simulation results were obtained from the Cadence Innovus digital system taped-out at 45 nm. Our simulation results show that the proposed algorithm satisfies timing constraints through a 30.6% reduction in wirelength.

Wire length optimization of VLSI circuits using IWO algorithm and its hybrid

PurposeAdvancement in optimization of VLSI circuits involves reduction in chip size from micrometer to nanometer level as well as fabrication of a billions of transistors in a single die where global routing problem remains significant with a trade-off of power dissipation and interconnect delay. This paper aims to solve the increased complexity in VLSI chip by minimization of the wire length in VLSI circuits using a new approach based on nature-inspired meta-heuristic, invasive weed optimization (IWO). Further, this paper aims to achieve maximum circuit optimization using IWO hybridized with particle swarm optimization (PSO).Design/methodology/approachThis paper projects the complexities of global routing process of VLSI circuit design in mapping it with a well-known NP-complete problem, the minimum rectilinear Steiner tree (MRST) problem. IWO meta-heuristic algorithm is proposed to meet the MRST problem more efficiently and thereby reducing the overall wire-length of interconnected nodes. Further, the proposed approach is hybridized with PSO, and a comparative analysis is performed with geosteiner 5.0.1 and existing PSO technique over minimization, consistency and convergence against available benchmark.FindingsThis paper provides high performance–enhanced IWO algorithm, which keeps in generating low MRST value, thereby successful wire length reduction of VLSI circuits is significantly achieved as evident from the experimental results as compared to PSO algorithm and also generates value nearer to geosteiner 5.0.1 benchmark. Even with big VLSI instances, hybrid IWO with PSO establishes its robustness over achieving improved optimization of overall wire length of VLSI circuits.Practical implicationsThis paper includes implications in the areas of optimization of VLSI circuit design specifically in the arena of VLSI routing and the recent developments in routing optimization using meta-heuristic algorithms.Originality/valueThis paper fulfills an identified need to study optimization of VLSI circuits where minimization of overall interconnected wire length in global routing plays a significant role. Use of nature-based meta-heuristics in solving the global routing problem is projected to be an alternative approach other than conventional method.

Quantifying the Impact of Monolithic 3D (M3D) Integration on L1 Caches

Monolithic 3D (M3D) integration has been recently introduced as a viable solution for fine-grained 3D integration. Since the conventional 3D integration uses relatively large micro-scale through-silicon-vias (TSVs), which causes large TSV area overhead, it is not cost-effective for small micro architectural blocks such as L1 caches. On the contrary, the M3D integration offers nano-scale monolithic inter-tier vias (MIVs) which are much smaller than TSVs. Thus, the M3D integration is known to be even feasible for 3D stacking of small micro architectural blocks, which reduces wire length of the blocks, leading to better performance and energy-efficiency. In this paper, we quantify the architectural impact (in terms of performance, power, temperature, and area) of the M3D integration for L1 caches. In our evaluation, the 8-layer stacked M3D L1 caches show 34.1~43.2 percent shorter access time than the 2D L1 cache. As a result, the M3D L1 caches improve the performance of SPEC CPU 2006 applications by 9.9 percent (up to 43.7 percent), on average, compared to the conventional 2D L1 caches. Additionally, the 8-layer stacked M3D L1 caches reduce dynamic energy and leakage power by 58.9 percent ~60.8 percent and 57.9~59.1 percent, respectively, compared to the 2D L1 cache. Additionally, though 3D stacking inevitably causes higher temperature than 2D baseline, since the M3D integration provides better heat dissipation as well as lower power consumption than the conventional TSV-3D, it reduces peak L1 cache temperature by up to 7.6°C, compared to the TSV-3D.

Lock Isolation Security Architecture for Reconfigurable Scanning Networks

<p indent=0mm>To protect the reconfigurable scanning network from the influence of unauthorized access, tampering of transmitted data by malicious instruments and sniffing, a lock isolation security structure is proposed. Firstly, the presented structure divides the instruments without security threat to each other into one group, and the groups can be accessed one by one via the isolated signals, which can prevent malicious instruments tampering and sniffing transmitted data. Secondly, the key instruments are protected by the lock segment insertion bit. The lock segment insertion bit can only be opened when multiple key values at specific positions are set to specific values (0, 1 sequence), which can increase the difficulty of unauthorized access. Besides, to reduce the hardware overhead, and the difficulty of place and route caused by excessive instrument groups, instrument grouping algorithm is proposed. The proposed algorithm firstly constructs an undirected graph based on the security relationship among instruments. Then the maximal independent sets of the undirected are obtained. In this way, the number of instrument groups is reduced greatly. Compared to other similar methodologies, the experimental results conducted on ITC 02 benchmark circuits show that the time consumption for opening the locking segment insertion bit of the proposed security structure increased by 7 times, and the average percentage reduction of area, power consumption and wire length is 3.81%, 9.02% and 4.55%, respectively.

Social learning discrete Particle Swarm Optimization based two-stage X-routing for IC design under Intelligent Edge Computing architecture

One of the core features of Intelligent Edge Computing (IEC) is real-time decision making, therefore low delay is more important for IC design under IEC architecture. And in very large scale integration routing, wirelength is one of the most important indexes affecting the final delay of the IC design. Therefore, this paper introduces the X-routing with more potential for wirelength optimization and the Steiner Minimum Tree (SMT), which is the best routing model in multi-terminal nets. Then, based on Particle Swarm Optimization (PSO) technique which has the strong global optimization ability in Soft Computing, an effective Two-Stage X-routing Steiner minimum tree construction algorithm is proposed. The proposed algorithm is divided into two stages: social learning discrete PSO searching and wirelength reduction. In the first stage, two excellent strategies are proposed to maintain a good balance between exploration and exploitation capabilities of the PSO technique: (1) Chaotic decreasing inertia weight combined with mutation operator is set to enhance the exploration capability. (2) A new social learning approach combined with crossover operator is designed to ensure the diverse evolution of the swarm while maintaining the exploitation capability. In the second stage, a strategy based on local topology optimization is proposed to further reduce the length of X-routing Steiner tree. Experiments show that the proposed algorithm can achieve the best wirelength optimization and has a strong stability, especially for large-scale SMT problem, so as to better satisfy the demand of low delay of IC design under IEC architecture.

Machine learning based effective linear regression model for TSV layer assignment in 3DIC

On the integration of 3D IC design, thermal management issues play a significant role. So, it is required to implement an effective approaches and solutions for integrating 3DIC. The TSV causes problems with the distinct coefficients of thermal expansion that induces mismatch strains and stresses. The major drawback of 3DIC is the thermal management issues which increases the power consumption through the current crowding, perhaps the temperature upraised by the slacked layers due to its heat generation. Several research has not been undergone in 3DIC utilizing machine learning approaches which is highly complicated. This paper firstly proposes an efficient ML model to achieve better reduction in wire length and temperature. An efficient linear regression model is preferred here in order to achieve significant performances in TSV layer assignment. The linear regression utilized gradient based approach where the error is predicted at every instance through tracing gradient cost function. An optimized TSV layer assignment is achieved with this flexible ELRM. The performance analysis of data shows that the proposed ELRM based TSV assignment achieved better wire length and temperature. The ISPD98 Circuit Benchmark Suite is utilized for result evaluation and it achieves improved TSV layer assignment through reducing wire length and temperature.

GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse-Grained Reconfigurable Architectures

Coarse-grained reconfigurable architectures (CGRAs) are expected to be used for embedded systems, Internet of Things (IoT) devices, and edge computing thanks to their high-energy efficiency and programmability. In essence, a CGRA is an array of numerous processing elements. To exploit this abundant computation resource, a compiler for CGRAs has to fulfill more tasks compared that for general-purpose processors. Therefore, many studies have proposed optimization methods, especially for application mapping, because the performance and energy efficiency strongly depend on optimization at compile time. However, many works focus only on performance improvement or resource minimization, although such optimization objectives are not always appropriate when considering various use cases. In this work, we propose GenMap, an application mapping framework using multiobjective optimization based on a genetic algorithm so that users can set optimization criteria as needed. Besides, it provides aggressive power optimization using our dynamic power model and leakage minimization technique. The proposed method is applied to three fabricated CGRA chips for evaluation. Experimental results show that GenMap achieves 15.7% reduction of wire length while keeping processing element utilization when compared with conventional methods. In addition, according to real chip experiments, 12.1%–46.8% of energy consumption is reduced, and up to $2\times $ speedup is archived for several architectures when compared with other two approaches.

Many-Tier Vertical GAAFET (V-FET) for Ultra-Miniaturized Standard Cell Designs Beyond 5 nm

The GAAFET (gate-all-around FET) is expected to replace FinFETs in future nodes due to its excellent channel controllability. It is also expected to be an impressive device due to its horizontal or vertical transistor structures. Vertical GAAFETs (V-FETs) are expected to be a promising device compared to horizontal GAAFETs (H-FETs) due to their structure, which allows area reduction and significant parasitic reduction. Besides, V-FETs are positioned on top of each other and thus allow more significant size reductions. Therefore, this paper studies the overall potential of many-tier V-FETs by investigating the essential design factors from the layout perspective. First, we study the factors that should be considered for designing many-tier V-FETs. Second, we propose an interconnect structure that maximizes the advantages of many-tier V-FETs. Third, we compare 2-tier V-FET standard cells to one-tier V-FET cells and visualize the advantages that many-tier V-FET cells provide. Our study shows that 2-tier V-FET standard cells provide a -35.6% area reduction with a cost of +16.5% wirelength and +13.2% parasitic capacitance increase compared to 1-tier V-FET cells. Compared to H-FETs and FinFETs, our cells show -50.1% area reductions with -0.3% wirelength reductions and -18.9% parasitic capacitance reductions. We emphasize that the design freedom to place transistors on top of each other and proper interconnect structures lead to ultra-scale miniaturized standard cell designs. We note that the increase in wirelength and capacitance is due to the vertical size increases and detours that must exist in the designs. Thus, careful circuit design is required to obtain the maximum advantages from V-FETs.

Enhanced Power and Ground Mesh Structure for IR-Drop Reduction

New enhanced power/ground mesh structure is presented for voltage drop (IR drop) reduction on power distribution network in integrated circuits (ICs). The new structure focuses on the length of the overall power/ground mesh wire pattern, reducing it by using a complex dotted line wire pattern instead of the usual mesh straps, which brings to wire length reduction on almost 40%, while via count on changed metal layer remained the same. Measurements of the voltage drop prove that with proposed mesh structure IR drop reduced about 76% for power net compared to standard mesh structure but runtime for mesh creation is increased due to more complex patterns. Proposed structure can be used in advanced technology nodes where IR drop phenomenon has become critical for performance of the ICs.

Optimization of thermal aware multilevel routing for 3D IC

Due to the technological advancements, the three dimensional Integrated Circuits become the most popular technology. But it has the major drawback of increased time consumption as well power consumption. This happens because of the increased wire length and routing path for connecting the components in chip. Thus it is essential to reduce the wire length for the purpose of enhancing the circuit speed and minimize the power dissipation. But there may be a chance of temperature rise due to the heat generated by the slacked layers which also needs to be reduced. Several traditional approaches have addressed the issues of temperature rise and layer assignment. But the utilization of through-silicon-via is considered. Thus a new stochastic based genetic algorithm is proposed in this work for reducing the thermal estimations. Also the length of wire can be reduced by determining the minimal path so as to connect the components. Both partitioning and routing process takes place in this approach. The performance of the proposed approach is analyzed using ISPD2008 dataset. Also the results of this stochastic based model are compared with the existing algorithm. The superiority of this proposed approach is proved with reduced wire length and temperature estimations.

RePlAce: Advancing Solution Quality and Routability Validation in Global Placement

The Nesterov’s method approach to analytic placement has recently demonstrated strong solution quality and scalability. We dissect the previous implementation strategy and show that solution quality can be significantly improved using two levers: 1) constraint-oriented local smoothing and 2) dynamic step size adaptation. We propose a new density function that comprehends local overflow of area resources; this enables a constraint-oriented local smoothing at per-bin granularity. Our improved dynamic step size adaptation automatically determines step size and effectively allocates optimization effort to significantly improve solution quality without undue runtime impact. Our resulting global placement tool, RePlAce, achieves an average of 2.00% half-perimeter wirelength (HPWL) reduction over all best known ISPD-2005 and ISPD-2006 benchmark results, and an average of 2.73% over all best known modern mixed-size (MMS) benchmark results, without any benchmark-specific code or tuning. We further extend our global placer to address routability, and achieve on average 8.50%–9.59% scaled HPWL reduction over previous leading academic placers for the DAC-2012 and ICCAD-2012 benchmark suites. To our knowledge, RePlAce is the first work to achieve superior solution quality across all the ISPD-2005, ISPD-2006, MMS, DAC-2012, and ICCAD-2012 benchmark suites with a single global placement engine.