Recursive Pyramid Algorithm Research Articles

BiRPN-YOLOvX: A weighted bidirectional recursive feature pyramid algorithm for lung nodule detection.

Lung cancer has the second highest cancer mortality rate in the world today. Although lung cancer screening using CT images is a common way for early lung cancer detection, accurately detecting lung nodules remains a challenged issue in clinical practice. This study aims to develop a new weighted bidirectional recursive pyramid algorithm to address the problems of small size of lung nodules, large proportion of background region, and complex lung structures in lung nodule detection of CT images. First, the weighted bidirectional recursive feature pyramid network (BiPRN) is proposed, which can increase the ability of network model to extract feature information and achieve multi-scale fusion information. Second, a CBAM_CSPDarknet53 structure is developed to incorporate an attention mechanism as a feature extraction module, which can aggregate both spatial information and channel information of the feature map. Third, the weighted BiRPN and CBAM_CSPDarknet53 are applied to the YOLOvX model for lung nodule detection experiments, named BiRPN-YOLOvX, where YOLOvX represents different versions of YOLO. To verify the effectiveness of our weighted BiRPN and CBAM_ CSPDarknet53 algorithm, they are fused with different models of YOLOv3, YOLOv4 and YOLOv5, and extensive experiments are carried out using the publicly available lung nodule datasets LUNA16 and LIDC-IDRI. The training set of LUNA16 contains 949 images, and the validation and testing sets each contain 118 images. There are 1987, 248 and 248 images in LIDC-IDRI's training, validation and testing sets, respectively. The sensitivity of lung nodule detection using BiRPN-YOLOv5 reaches 98.7% on LUNA16 and 96.2% on LIDC-IDRI, respectively. This study demonstrates that the proposed new method has potential to help improve the sensitivity of lung nodule detection in future clinical practice.

Recursive Pyramid Algorithm-Based Discrete Wavelet Transform for Reactive Power Measurement in Smart Meters

Measurement of the active, reactive, and apparent power is one of the most fundamental tasks of smart meters in energy systems. Recently, a number of studies have employed the discrete wavelet transform (DWT) for power measurement in smart meters. The most common way to implement DWT is the pyramid algorithm; however, this is not feasible for practical DWT computation because it requires either a log N cascaded filter or O (N) word size memory storage for an input signal of the N-point. Both solutions are too expensive for practical applications of smart meters. It is proposed that the recursive pyramid algorithm is more suitable for smart meter implementation because it requires only word size storage of L × Log (N-L), where L is the length of filter. We also investigated the effect of varying different system parameters, such as the sampling rate, dc offset, phase offset, linearity error in current and voltage sensors, analog to digital converter resolution, and number of harmonics in a non-sinusoidal system, on the reactive energy measurement using DWT. The error analysis is depicted in the form of the absolute difference between the measured and the true value of the reactive energy.

Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT

In this paper, we present a modular and pipeline architecture for lifting-based multilevel 2-D DWT, without using line-buffer and frame-buffer. Overall area-delay product is reduced in the proposed design by appropriate partitioning and scheduling of the computation of individual decomposition-levels. The processing for different levels is performed by a cascaded pipeline structure to maximize the hardware utilization efficiency (HUE). Moreover, the proposed structure is scalable for high-throughput and area-constrained implementation. We have removed all the redundancies resulting from decimated wavelet filtering to maximize the HUE. The proposed design involves <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> pyramid algorithm (PA) units and one recursive pyramid algorithm (RPA) unit, where <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> = <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> , <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> =⌈log <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P̅</i> ⌉ and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> is the input block size, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</i> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> , respectively, being the height and width of the image. The entire multilevel DWT is computed by the proposed structure in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MR</i> cycles. The proposed structure has <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</i> (8 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> ×2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> ) cycles of output latency, which is very small compared to the latency of the existing structures. Interestingly, the proposed structure does not require any line-buffer or frame-buffer, unlike the existing folded structures which otherwise require a line-buffer of size <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</i> ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> ) and frame-buffer of size <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</i> ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</i> /2× <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> /2) for multilevel 2-D computation. Instead of those buffers, the proposed structure involves only local registers and RAM of size <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</i> ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> ). The saving of line-buffer and frame-buffer achieved by the proposed design is an important advantage, since the image size could very often be as large as 512 × 512. From the simulation results we find that, the proposed scalable structure offers better slice-delay-product (SDP) for higher throughput of implementation since the on-chip memory of this structure remains almost unchanged with input block size. It has 17% less SDP than the best of the corresponding existing structures on average, for different input-block sizes and image sizes. It involves 1.92 times more transistors, but offers 12.2 times higher throughput and consumes 52% less power per output (PPO) compared to the other, on average for different input sizes.

VLSI Implementation of Lifting Wavelet Transform of JPEG2000 with Efficient RPA(Recursive Pyramid Algorithm) Realization

This paper presents an efficient VLSI architecture of biorthogonal (9,7)/(5,3) lifting based discrete wavelet transform that is used by lossy or lossless compression of JPEG2000. To improve hardware utilization of RPA (Recursive Pyramid Algorithm) implementation, we make the filter that is responsible for row operations of the first level perform both column operations and row operations of the second and following levels. As a result, the architecture has 66.7--88.9% hardware utilization. It requires 9 multipliers, 12 adders, and 12N line memories for N × N image, which is smaller hardware complexity compared to that of other architectures with comparable throughput.

Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method

In this paper, three generic RAM-based architectures are proposed to efficiently construct the corresponding two-dimensional architectures by use of the line-based method for any given hardware architecture of one-dimensional (1-D) wavelet filters, including conventional convolution-based and lifting-based architectures. An exhaustive analysis of two-dimensional architectures for discrete wavelet transform in the system view is also given. The first proposed architecture is for 1-level decomposition, which is presented by introducing the categories of internal line buffers, the strategy of optimizing the line buffer size, and the method of integrating any 1-D wavelet filter. The other two proposed architectures are for multi-level decomposition. One applies the recursive pyramid algorithm directly to the proposed 1-level architecture, and the other one combines the two previously proposed architectures to increase the hardware utilization. According to the comparison results, the proposed architecture outperforms previous architectures in the aspects of line buffer size, hardware cost, hardware utilization, and flexibility.

Two fast architectures for the direct 2-D discrete wavelet transform

We propose two architectures for the direct two-dimensional (2-D) discrete wavelet transform (DWT). The first one is based on a modified recursive pyramid algorithm (MRPA) and performs a nonstandard decomposition (i.e., Mallat's (1989) tree) of an N/spl times/N image in approximately 2N/sup 2//3 clock cycles (ccs). This result consistently speeds up other known architectures that commonly need approximately N/sup 2/ ccs. Furthermore, the proposed architecture is simpler than others in terms of hardware complexity. Subsequently, we show how symmetric/anti-symmetric properties of linear-phase wavelet filter bases can be exploited in order to further reduce the VLSI area. This is used to design a second architecture that provides one processing unit for each level of decomposition (pipelined approach) and performs a decomposition in approximately N/sup 2//2 ccs. In many practical cases, even this architecture is simpler than general MRPA-based devices (having only one processing unit).

A Programmable Parallel VLSI Architecture for 2-D Discrete Wavelet Transform

Many VLSI architectures for computing the discrete wavelet transform (DWT) were presented, but the parallel input data sequence and the programmability of the 2-D DWT were rarely mentioned. In this paper, we present a parallel-processing VLSI architecture to compute the programmable 2-D DWT, including various wavelet filter lengths and various wavelet transform levels. The proposed architecture is very regular and easy for extension. To eliminate high frequency components, the pixel values outside the boundary of the image are mirror-extended as the symmetric wavelet transform (SWT) and the mirror-extension is realized via the routing network. Owing to the property of the parallel processing, we adopt the row-based recursive pyramid algorithm (RPA), similar to 1-D RPA, as the data scheduling. This design has been implemented and fabricated in a 0.35 mm 1P4M CMOS technology and the working frequency is 50 MHz. The chip size is about 5200 mm × 2500 mm. For a 256 × 256 image, the chip can perform 30 frames per second with the filter length varying from 2 to 20 and with various levels. The proposed architecture is suitable for real-time applications such as JPEG 2000.

Handling borders in systolic architectures for the 1-D discrete wavelet transform for perfect reconstruction

We propose a modified systolic architecture that implements the 1-D discrete wavelet transform (DWT) on the basis of the recursive pyramid algorithm (RPA) while correctly managing the border problem and obtaining perfect reconstruction. All the architectures so far described in the literature do not explicitly address the handling of borders and usually assume a zero-padding extension. The RPA makes heavy use of this assumption, which produces very efficient systolic architectures. It is, however, well known that the zero-padding extension does not allow perfect recovery of the original signal, if we compute exactly N coefficients. More coefficients are required either in the forward or in the inverse transform, and their production within the RPA scheme lowers the efficiency of the systolic architecture to a minimum. We introduce a modified RPA working on an extended transform with a compressed schedule that restores good values of efficiency (EC-RPA). We also propose a second version of RPA based on a periodic extension of the signal and of the transform (PE-RPA) that achieves perfect reconstruction by computing exactly N DWT coefficients. A reduced version of the second algorithm (R-PE-RPA) is tailored to the efficient computations of a fixed number of levels in the transform. The VLSI complexity of the management of borders is analyzed through synthesis from a VHDL description of the three algorithms. Synthesis results show that the controller required for PE-RPA can be as large as a ten-tap array. R-PE-RPA instead requires half this area. In both cases, the controller complexity scales sublinearly with the length of the input.

VLSI architectures for the discrete wavelet transform

A class of VLSI architectures based on linear systolic arrays, for computing the 1-D Discrete Wavelet Transform (DWT), is presented. The various architectures of this class differ only in the design of their routing networks, which could be systolic, semisystolic, or RAM-based. These architectures compute the Recursive Pyramid Algorithm, which is a reformulation of Mallat's pyramid algorithm for the DWT. The DWT is computed in real time (running DWT), using just N/sub w/(J-1) cells of storage, where N/sub w/ is the length of the filter and J is the number of octaves. They are ideally suited for single-chip implementation due to their practical I/O rate, small storage, and regularity. The N-point 1-D DWT is computed in 2N cycles. The period can be reduced to N cycles by using N/sub w/ extra MAC's. Our architectures are shown to be optimal in both computation time and in area. A utilization of 100% is achieved for the linear array. Extensions of our architecture for computing the M-band DWT are discussed. Also, two architectures for computing the 2-D DWT (separable case) are discussed. One of these architectures, based on a combination of systolic and parallel filters, computes the N/sup 2/-point 2-D DWT, in real time, in N/sup 2/+N cycles, using 2NN/sub w/ cells of storage. >

The recursive pyramid algorithm for the discrete wavelet transform

The recursive pyramid algorithm (RPA) is a reformulation of the classical pyramid algorithm (PA) for computing the discrete wavelet transform (DWT). The RPA computes the N-point DWT in real time (running DWT) using just L(log N/spl minus/1) words of storage, as compared with O(N) words required by the PA. L is the length of the wavelet filter. The RPA is combined with the short-length FIR filter algorithms to reduce the number of multiplications and additions. >