Rectilinear Steiner Minimal Tree Research Articles

NN-Steiner: A Mixed Neural-Algorithmic Approach for the Rectilinear Steiner Minimum Tree Problem

Recent years have witnessed rapid advances in the use of neural networks to solve combinatorial optimization problems. Nevertheless, designing the "right" neural model that can effectively handle a given optimization problem can be challenging, and often there is no theoretical understanding or justification of the resulting neural model. In this paper, we focus on the rectilinear Steiner minimum tree (RSMT) problem, which is of critical importance in IC layout design and as a result has attracted numerous heuristic approaches in the VLSI literature. Our contributions are two-fold. On the methodology front, we propose NN-Steiner which is a novel mixed neural-algorithmic framework for computing RSMTs that leverages the celebrated PTAS algorithmic framework of Arora to solve this problem (and other geometric optimization problems). Our NN-Steiner replaces key algorithmic components within Arora's PTAS by suitable neural components. In particular, NN-Steiner only needs four neural network (NN) components that are called repeatedly within an algorithmic framework. Crucially, each of the four NN components is only of bounded size independent of input size, and thus easy to train. Furthermore, as the NN component is learning a generic algorithmic step, once learned, the resulting mixed neural-algorithmic framework generalizes to much larger instances not seen in training. Our NN-Steiner, to our best knowledge, is the first neural architecture of bounded size that has capacity to approximately solve RSMT (and variants). On the empirical front, we show how NN-Steiner can be implemented and demonstrate the effectiveness of our resulting approach, especially in terms of generalization, by comparing with state-of-the-art methods (both neural and non-neural based).

Construction of All Multilayer Monolithic RSMTs and Its Application to Monolithic 3D IC Routing

Monolithic three-dimensional (M3D) integration allows ultra-thin silicon tier stacking in a single package. The high-density stacking is acquiring interest and is becoming more popular for smaller footprint areas, shorter wirelength, higher performance, and lower power consumption than the conventional planar fabrication technologies. The physical design of M3D integrated circuits requires several design steps, such as three-dimensional (3D) placement, 3D clock-tree synthesis, 3D routing, and 3D optimization. Among these, 3D routing is significantly time consuming due to countless routing blockages. Therefore, 3D routers proposed in the literature insert monolithic interlayer vias (MIVs) and perform tier-by-tier routing in two substeps. In this article, we propose an algorithm to build a routing topology database (DB) used to construct all multilayer monolithic rectilinear Steiner minimum trees on the 3D Hanan grid. To demonstrate the effectiveness of the DB in various applications, we use the DB to construct timing-driven 3D routing topologies and perform congestion-aware global routing on 3D designs. We anticipate that the algorithm and the DB will help 3D routers reduce the runtime of the MIV insertion step and improve the quality of the 3D routing.

A Very Large-Scale Integration Global Routing Optimization Model for Hybrid Physarum Bionetworks

Interconnection of billion transistors in a single layer of a die with the advent of the nanometer regime imposes a great challenge to handle the increased complexity, particularly in the global routing of the Very Large-Scale Integration (VLSI) physical design phase which involves distinct optimization in the computation of overall interconnect wire-length. In classical graph theory, the VLSI global routing problem can be mapped as a Rectilinear Steiner Minimal Tree (RSMT) Problem, which in itself is an NP-complete problem. The use of metaheuristics in solving this problem plays a major role where Ant Colony Optimization (ACO) and Particle Swarm Optimization (PSO) proved to be efficient algorithms. Both algorithms face certain limitations and inconsistencies in determining maximum optimization. A new optimization algorithm with insight from the biological activity of microorganisms has been proposed in this paper which is based on the behavior of the unicellular organism Physarum Polycephalum aiming at minimizing the wire length of VLSI interconnects. The paper further explores a new hybridization technique employing the use of Physarum BioNetwork and Particle Swarm Optimization together where PSO generate better possible Steiner’s in the initial stage for the final process using Physarum BioNetwork to ensure better convergence. Complexity analysis of the proposed algorithm has been performed and the simulation results achieved greater efficiency when compared with the conventional PSO algorithm and available industry benchmark over-optimizing Global Routing problem in VLSI design.

Optimization of the multi-level steam production and supply in industrial parks

Steam is an important medium for energy transmission in industrial parks. For providing steam to multiple users, it is key to determine the optimal number of steam levels in the design of steam system. With the increasing number of steam levels, the energy demand and supply can be better matched but the investment of steam pipeline network increases. In this paper, this trade-off is solved by a two-stage method. In the first step, a mixed-integer nonlinear programming (MINLP) model is established to minimize the total cost of the steam system of the industrial park, while a simple pipeline network optimization model is involved. The optimal scheme of steam production including the number of steam levels can be obtained automatically. In the second step, GeoSteiner algorithm is used for solving Rectilinear Steiner Minimum Tree (RSMT) model to further optimize the pipeline network separately. In a case study, the optimal number of steam levels is 3. The total annual cost (TAC) of the optimal steam system is 11.4%, 5.28%, and 1.43% lower than the schemes with the lowest pipeline network cost (1 level of steam), the best matching between heat supply and heat demand (6 levels of steam), and the largest electricity generation capacity (4 levels of steam), respectively. The sensitivity analysis indicates that the overall heat load required by consumers and the distance between the energy station and consumers can make a difference to the optimal number of steam levels.

Optimization of Pipeline Network Layout for Multiple Heat Sources Distributed Energy Systems Considering Reliability Evaluation

Due to the target of carbon neutrality, energy saving has become more important than ever. At the same time, the widespread use of distributed energy systems and the regional utilization of industrial waste heat leads to the existence of multiple heat sources in an area. Therefore, how to design an economical and reliable pipeline network to meet energy-saving demand under multiple heat source conditions becomes a problem. In this work, an optimization method is established to determine the optimal pipeline network topology with minimum total annual cost. In this optimization method, Star tree algorithm, Kruskal algorithm and GeoSteiner algorithm are combined with a linear programming model to establish a distributed energy pipeline network for multiple heat sources. The model incorporates Euclidean Steiner Minimum Tree and Rectilinear Steiner Minimum Tree in the consideration of the topology optimization of Distributed Energy System pipeline networks. Four pipeline network topologies, STAR, Minimum Spanning Tree, Euclidean Steiner Minimum Tree and Rectilinear Steiner Minimum Tree, are evaluated in this paper from economic and reliability perspectives. A case extracted from a real industrial park where steam is the medium is used to prove the validity of the model. The optimization results show that a Euclidean Steiner Minimum Tree pipeline network has a lower total annual cost than three other types of pipeline network and ranks second in reliability. Considering the comprehensive economy and reliability, ESMT is the optimal pipeline network type of distributed energy system with steam as the medium.

Wire length optimization of VLSI circuits using IWO algorithm and its hybrid

PurposeAdvancement in optimization of VLSI circuits involves reduction in chip size from micrometer to nanometer level as well as fabrication of a billions of transistors in a single die where global routing problem remains significant with a trade-off of power dissipation and interconnect delay. This paper aims to solve the increased complexity in VLSI chip by minimization of the wire length in VLSI circuits using a new approach based on nature-inspired meta-heuristic, invasive weed optimization (IWO). Further, this paper aims to achieve maximum circuit optimization using IWO hybridized with particle swarm optimization (PSO).Design/methodology/approachThis paper projects the complexities of global routing process of VLSI circuit design in mapping it with a well-known NP-complete problem, the minimum rectilinear Steiner tree (MRST) problem. IWO meta-heuristic algorithm is proposed to meet the MRST problem more efficiently and thereby reducing the overall wire-length of interconnected nodes. Further, the proposed approach is hybridized with PSO, and a comparative analysis is performed with geosteiner 5.0.1 and existing PSO technique over minimization, consistency and convergence against available benchmark.FindingsThis paper provides high performance–enhanced IWO algorithm, which keeps in generating low MRST value, thereby successful wire length reduction of VLSI circuits is significantly achieved as evident from the experimental results as compared to PSO algorithm and also generates value nearer to geosteiner 5.0.1 benchmark. Even with big VLSI instances, hybrid IWO with PSO establishes its robustness over achieving improved optimization of overall wire length of VLSI circuits.Practical implicationsThis paper includes implications in the areas of optimization of VLSI circuit design specifically in the arena of VLSI routing and the recent developments in routing optimization using meta-heuristic algorithms.Originality/valueThis paper fulfills an identified need to study optimization of VLSI circuits where minimization of overall interconnected wire length in global routing plays a significant role. Use of nature-based meta-heuristics in solving the global routing problem is projected to be an alternative approach other than conventional method.

Efficient VLSI routing algorithm employing novel discrete PSO and multi-stage transformation

For routing industrial circuits, the Steiner minimal tree (SMT) model can be applied in different routing problems, such as wirelength optimization, congestion reduction, and delay optimization. In this paper, an efficient VLSI routing algorithm employing novel discrete particle swarm optimization (PSO) and multi-stage transformation is proposed to build two types of SMT, including X-architecture Steiner minimal tree and rectilinear Steiner minimal tree. Firstly, to simultaneously handle two types of SMT problems, an effective encoding strategy is proposed to be more suitable for PSO and thus it can overcome the difficulty of designing different algorithms for different routing architectures. Secondly, a multi-stage transformation strategy is presented to expand the search space of the proposed algorithm and accelerate the convergence speed of the proposed algorithm. Various combinations of multi-stage transformation strategies have been tested to highlight the best combination. Furthermore, the various genetic operators combined with union-find data structure strategy are proposed to construct the novel and effective discrete particle update formula. Experimental simulation results on industrial circuits show that the proposed algorithm can get the best solutions among the existing algorithms.

Memory and I/O optimized rectilinear steiner minimum tree routing for VLSI

As the size of devices are scaling down at rapid pace, the interconnect delay play a major part in performance of IC chips. Therefore minimizing delay and wire length is the most desired objective. FLUTE (Fast Look-Up table) presented a fast and accurate RSMT (Rectilinear Steiner Minimum Tree) construction for both smaller and higher degree net. FLUTE presented an optimization technique that reduces time complexity for RSMT construction for both smaller and larger degree nets. However for larger degree net this technique induces memory overhead, as it does not consider the memory requirement in constructing RSMT. Since availability of memory is very less and is expensive, it is desired to utilize memory more efficiently which in turn results in reducing I/O time (i.e. reduce the number of I/O disk access). The proposed work presents a Memory Optimized RSMT (MORSMT) construction in order to address the memory overhead for larger degree net. The depth-first search and divide and conquer approach is adopted to build a Memory optimized tree. Experiments are conducted to evaluate the performance of proposed approach over existing model for varied benchmarks in terms of computation time, memory overhead and wire length. The experimental results show that the proposed model is scalable and efficient.

Memory and I/O Optimized Rectilinear Steiner Minimum Tree Routing For VLSI

As the size of devices are scaling down at rapid pace, the interconnect delay play a major part in performance of IC chips. Therefore minimizing delay and wire length is the most desired objective. FLUTE (Fast Look-Up table) presented a fast and accurate RSMT (Rectilinear Steiner Minimum Tree) construction for both smaller and higher degree net. In this paper, FLUTE presented an optimization technique that reduces time complexity for RSMT construction for both smaller and larger degree nets. However for larger degree net this technique induces memory overhead, as it does not consider the memory requirement in constructing RSMT. Since availability of memory is very less and is expensive, it is desired to utilize memory more efficiently which in turn results in reducing I/O time (i.e. reduce the number of I/O disk access). The proposed work presents a Memory Optimized RSMT (MORSMT) construction in order to address the memory overhead for larger degree net. The depth-first search and divide and conquer approach is adopted to build a Memory optimized tree. Experiments are conducted to evaluate the performance of proposed approach over existing model for varied benchmarks in term of computation time, memory overhead and wire length. The experimental results show that the proposed model is scalable and efficient.

Obstacle aware delay optimized rectilinear steiner minimum tree routing

<p><span>This work presents a method to solve the problem of constructing Rectilinear Steiner Minimum Tree (RSMT) for a group of pins in the presence of obstacles. In modern </span><span>very large-scale integrated circuit</span><span> (VLSI) designs, the obstacles, generally blocks the metal and the device layer. Therefore routing on top of blockage is a possible solution but buffers cannot be placed over the obstacle. Modern VLSI design OARSMT construction has long wire length, which results in signal violation. To address this issue a slew constraint interconnect need to be considered in routing over obstacle. This is called the Obstacle-Avoiding Rectilinear Steiner minimum trees (OARSMT) problem with slew constraints over obstacles. The drawback of traditional OARSMT is that they only consider slew constraint, and delay constraints are neglected. It induces high routing resources overhead due to buffer insertion and does not solve global routing solution. This work presents an Obstacle Aware Delay Optimized Rectilinear Steiner Minimum Tree (OADORSMT) Routing to address the delay, slew constraint and reduce the routing resources. Experiments are conduced to evaluate the performance of proposed approach over existing approach in term of wire length and worst negative slack. The experiments are conducted for small and large nets considering fixed and varied obstacles and outcome shows the proposed efficiency over existing approaches. The OADORSMT is designed in such a way where it can be parallelized to obtain better efficiency.</span></p>

PORA: A Physarum-inspired obstacle-avoiding routing algorithm for integrated circuit design

The plasmodium of Physarum polycephalum, a large, amoeboid cell, has attracted much attention recently due to its intelligent behaviors in pathfinding, danger avoidance, and network construction. Inspired by the biological behaviors of this primitive organism, in this study, we explore the optimization capability of Physarum polycephalum systematically and present the first Physarum-inspired obstacle-avoiding routing algorithm for the physical design of integrated circuits. We simulate the foraging behaviors of Physarum polycephalum using a novel nutrition absorption/consumption mathematical model, thereby presenting an efficient routing tool called Physarum router. With the proposed routing approach, for a given set of pin vertices and a given set of on-chip functional modules, a rectilinear Steiner minimal tree connecting all the pin vertices while avoiding the blockage of functional modules can be constructed automatically. Furthermore, several heuristics including a divide-and-conquer strategy, a non-pin leaf node pruning strategy, a dynamic parameter strategy, etc., are integrated into the proposed algorithm to fundamentally improve the performance of the Physarum router. Simulation results on multiple benchmarks confirm that the proposed algorithm leads to shorter wirelength compared with several state-of-the-art methods.

Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid and Its Applications to VLSI Design

A rectilinear Steiner minimum tree (RSMT) is a rectilinear Steiner tree connecting a given set of pins with the shortest wirelength. RSMT construction is one of the most frequently used algorithms in the physical design automation, including floorplanning, placement, routing, and interconnect estimation and optimization. Thus, efficient algorithms to construct RSMTs have been developed for many years in academia and industry. Unfortunately, RSMT construction is an NP-hard problem, so even a fast RSMT construction algorithm, such as GeoSteiner is too slow to use in physical design automation tools. FLUTE, a fast lookup-table-based RSMT construction algorithm, builds and uses a routing topology database to quickly construct RSMTs. In this paper, we present an algorithm to build a database (ARSMT DB) to construct all RSMTs on the Hanan grid for a given set of pins. ARSMT DB constructs all RSMTs in almost no time, so numerous applications could use it for various purposes. We apply the ARSMT DB to two applications, timing-driven RSMT construction and congestion-aware global routing, and show that the ARSMT DB can help reduce source-to-critical-sink lengths, source-to-critical-sink delays, and routing congestion significantly. Since the size of the original ARSMT DB is too large, we present techniques to reduce the database size.

SALT: Provably Good Routing Topology by a Novel Steiner Shallow-Light Tree Algorithm

In a weighted undirected graph, a spanning/Steiner shallow-light tree (SLT) simultaneously approximates: 1) shortest distances from a root to the other vertices and 2) the minimum tree weight. The Steiner SLT has been proved to be exponentially lighter than the spanning one. In this paper, we propose a novel Steiner SLT construction method called Steiner SLT (SALT), which is efficient and has the tightest bound over all the state-of-the-art general-graph SLT algorithms. Applying SALT to Manhattan space offers a smooth tradeoff between rectilinear Steiner minimum tree and rectilinear Steiner minimum arborescence for VLSI routing. The adaption also reduces the time complexity from O(n2) to O(n log n). Besides, several effective post-processing methods, including safe refinement and shallowness-constrained edge substitution, are proposed to further improve the result. The experimental results show that SALT can achieve not only short path lengths and wirelength but also small delay, compared to both classical and recent routing tree construction methods.

Optimal urban sewer layout design using Steiner tree problems

ABSTRACTThis article introduces a novel method using mixed-integer linear programming for optimizing sewer layouts. The research concept was obtained from the obstacle-avoiding rectilinear Steiner minimal tree technique in integrated circuit routing design. The Steiner nodes serve as optional nodes to link each sewer discharge node and flow to sinks on an optimal sewer layout. Those nodes are utilized for minimizing the total cost required for constructing pipes. All the nonlinear constraints and the objective function are transformed into a simple linear format. The optimization model analysed three types of objective function conditions—solely considering the pipe cost, solely considering the ground-cutting cost, and combining both considerations—to illustrate the importance of considering all conditions to obtain an optimal sewer layout design. The proposed optimization model can save more than 38.83% of the cost required to realize the expert’s manual sewer layout design.

Minimum rectilinear Steiner tree of n points in the unit square

Chung and Graham conjectured (in 1981) that n points in the unit square [0,1]2 can be connected by a rectilinear Steiner tree of length at most n+1. Here we confirm this conjecture for small values of n, and for some new infinite sequences of values of n (but not for all n). As an interesting byproduct we obtain close rational approximations of n from below, for those n.

Minimizing path lengths in rectilinear Steiner minimum trees with fixed topology

Given a Steiner tree G interconnecting a set of points T located in Rd, the Rectilinear Steiner Tree Problem with Fixed Topology is to compute coordinates for the remaining nodes V(G)∖T minimizing the l1-length of G. Considering the secondary objective of minimizing root-to-leave distances, we prove the existence of optimum coordinates such that among all minimal length solutions all the root-to-leave distances are minimized simultaneously, and we present an O(n⋅d) time algorithm.

Analysis of gene copy number changes in tumor phylogenetics.

BackgoundEvolution of cancer cells is characterized by large scale and rapid changes in the chromosomal landscape. The fluorescence in situ hybridization (FISH) technique provides a way to measure the copy numbers of preselected genes in a group of cells and has been found to be a reliable source of data to model the evolution of tumor cells. Chowdhury et al. (Bioinformatics 29(13):189–98, 23; PLoS Comput Biol 10(7):1003740, 24) recently develop a computational model for tumor progression driven by gains and losses in cell count patterns obtained by FISH probes. Their model aims to find the rectilinear Steiner minimum tree (RSMT) (Chowdhury et al. in Bioinformatics 29(13):189–98, 23) and the duplication Steiner minimum tree (DSMT) (Chowdhury et al. in PLoS Comput Biol 10(7):1003740, 24) that describe the progression of FISH cell count patterns over its branches in a parsimonious manner. Both the RSMT and DSMT problems are NP-hard and heuristics are required to solve the problems efficiently.MethodsIn this paper we propose two approaches to solve the RSMT problem, one inspired by iterative methods to address the “small phylogeny” problem (Sankoff et al. in J Mol Evol 7(2):133–49, 27; Blanchette et al. in Genome Inform 8:25–34, 28), and the other based on maximum parsimony phylogeny inference. We further show how to extend these heuristics to obtain solutions to the DSMT problem, that models large scale duplication events.ResultsExperimental results from both simulated and real tumor data show that our methods outperform previous heuristics (Chowdhury et al. in Bioinformatics 29(13):189–98, 23; Chowdhury et al. in PLoS Comput Biol 10(7):1003740, 24) in obtaining solutions to both RSMT and DSMT problems.ConclusionThe methods introduced here are able to provide more parsimony phylogenies compared to earlier ones which are consider better choices.

A heuristic for constructing a rectilinear Steiner tree by reusing routing resources over obstacles

The obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) problem is a hot topic in very-large-scale integration physical design. In practice, most of the obstacles occupy the device layer and certain lower metal layers. Therefore, we can place wires on top of the obstacles. To maximize routing resources over obstacles, we propose a heuristic for constructing a rectilinear Steiner tree with slew constraints. Our algorithm adopts an extended rectilinear full Steiner tree grid as the routing graph. We mark two types of Steiner point candidates, which are used for constructing Steiner trees and refining solutions. A shortest path heuristic variant is designed for constructing Steiner trees and it takes into account slew constraint by inhibiting growth. Furthermore, we use a pre-computed strategy to avoid calculating slew rate repeatedly. Experimental results show that our algorithm maximizes routing resources over obstacles and saves routing resources outside obstacles. Compared with the conventional OARSMT algorithm, our algorithm reduces the wire length outside obstacles by as much as 18.74% and total wire length by as much as 6.03%. Our algorithm improves the latest related algorithm by approximately 2% in terms of wire length within a reasonable running time. Additionally, calculating the slew rate only accounts for approximately 15% of the total runing time.

Obstacle-Avoiding Rectilinear SteinerMinimum Tree: A Survey

Rectilinear Steiner Minimum Tree (RSMT) is one of the global routing techniques in VLSI design, where the tree spans a given set of pins by reaching each of them either vertically or horizontally.While constructing such RSMTs, there can be many obstacles.There are many research works done in order to construct RSMTs which aredevoid of obstacles. Some of the recent research works are considered in this paper to understand the problem and to learn the available solutions.It covers and compares different approaches and methodologies which are used to find OARSMT. Some of the different approaches discussed here are Geo-Steiner approach, Maze routing method, Top-down partitioning approach and Greedy heuristic method.Comparison of these algorithms in accordance with their speed, efficiency, resources used and other pros and cons are also listed as a part of this work. A table listing the experimental results ismadeto realize the actual performance of different algorithms.

Efficient Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Geometric Reduction

Given a set of pin-vertices, an obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) connects all the pin-vertices possibly through Steiner points using vertical and horizontal segments with the minimal wirelength and without intersecting any obstacle. To deal with multiple routing layers and preferred routing orientations, we consider the multilayer obstacle-avoiding rectilinear Steiner minimal tree (ML-OARSMT) problem and the obstacle-avoiding preferred direction Steiner tree (OAPD-ST) problem. First, we prove that the multilayer case is theoretically different from the 2D one, and propose a reduction to transform a multilayer instance into a 3D instance. Based on the reduction, we apply computational geometry techniques to develop an efficient algorithm, utilizing existing OARSMT heuristics, for the ML-OARSMT problem and the OAPD-ST problem. Furthermore, we develop an advanced Steiner point selection to avoid inferior Steiner points and to improve the solution quality. Experimental results show that our algorithm provides a solution with excellent quality and has a significant speed-up compared to previously known results.