Rectangular Dualization Research Articles

Search Strategies to Solve the Complex-Triangle Elimination (CTE) Problem

This paper addresses the Complex-Triangle Elimination (CTE) problem of rectangular dualization approach in VLSI floor-planning. Rectangular dualization, where each module is realized as a rectangular area, is an important approach in VLSI floor-planning. It is known that if the input adjacency graph contains a complex triangle, i.e., a cycle of three edges that is not a face, then its rectangular dual does not exist. Elimination of complex triangles, therefore, becomes essential before constructing a floor plan. There are two versions of the CTE problem—that of weighted adjacency graphs, and of unweighted adjacency graphs. The weighted CTE problem is known to be NP-complete. Recently it has been proved that the unweighted CTE problem is also NP-complete [1]. In this paper we first present a greedy heuristic algorithm to solve the unweighted CTE problem. We then show, with the help of an example, that the greedy algorithm fails to produce an optimal solution in certain cases. Since Simulated Annealing (SA) is an effective technique to solve computationally hard minimization problems, we implemented SA based schemes to solve both the unweighted and weighted CTE problem. We also implemented three valley descending algorithms each for the weighted and the unweighted CTE problem. Results show that for the unweighted CTE problem the valley descending schemes converge much faster. A possible explanation is—the state space of the unweighted CTE problem is monotonous. However, this is yet to be proved (or disproved). In case of weighted CTE problem the SA based schemes produce better results, whereas the valley descending schemes get stuck at a sub-optimal solution. This is possibly because though the search space of the unweighted CTE problem is monotonous, that of the weighted CTE problem is not. All the schemes were tested with 25 randomly generated problem instances of various sizes.

Slicible rectangular graphs and their optimal floorplans

Rectangular dualization method of floorplanning usually involves topology generation followed by sizing. Slicible topologies are often preferred for their simplicity and efficiency. While slicible topologies can be obtained efficiently, existing linear-time algorithms for topology generation from a given rectangular graph does not guarantee slicible topologies even if one exists. Moreover, the class of rectangular graphs, known as inherently nonslicible graphs, do not have any slicible topologies. In this article, new tighter sufficiency conditions for slicibility of rectangular graphs are postulated and utilized in the generation of area-optimal floorplans. These graph-theoretic conditions not only capture a larger class of slicible rectangular graphs but also help in reducing the total effort for topology generation, and in solving problems of larger size.

A unified approach to topology generation and optimal sizing of floorplans

Existing algorithms for floorplan topology generation by rectangular dualization usually do not consider sizing issues. In this paper, given a rectangularly dualizable adjacency graph and a set of aspect ratios of the modules, a topology which is likely to yield an optimally sized floorplan, is produced first in a top-down fashion by an AI-based search technique with novel heuristic estimates based on size parameters. It is shown that for any rectangular graph, there exists a feasible topology using only either straight or Z-cutlines recursively within a bounding rectangle. The significance of this result is four-fold: (1) considerable acceleration of the heuristic search, (2) topology generation with minimal number of nonslice cores, (3) guaranteed safe routing order without addition of pseudo modules, and (4) design of an efficient bottom-up heuristic for optimal sizing. Experimental results show that this integrated method elegantly solves floorplan optimization problem for general including inherently nonslicible adjacency graphs.

Rectangular dualization and rectangular dissections

Rectangular dualization refers to finding a dual of a planar graph, that can be drawn in the form of a rectangular dissection; it has applications in architectural design and in the floorplanning of VLSI ICs. The authors present properties of rectangular dissections and discuss two related topics: (1) a problem of enumerating without repetitions all rectangular duals of a graph; and (2) transformations of rectangular dissections. The authors have developed a fast algorithm for enumerating rectangular duals that is based on a limited set of possible local changes in the structure of a rectangular dissection. A second procedure for systematically generating all rectangular duals of a graph is developed from the notion of partitioning the sets of rectangular dissections into disjoint subsets. >

Algorithms for floorplan design via rectangular dualization

A rectangular floorplan construction problem is approached from a graph-theoretical view. The study is based on a reduction of the rectangular dualization problem to a matching problem on bipartite graphs. This opens the way to applying traditional graph-theoretic methods and algorithms to floorplanning. Another result is a method for generating alternative rectangular duals, such that a proposed floorplan can be optimized by a sequence of iterative transformations. This approach is made more practical than others, by assuming that the given structure graph can be modified to force it to admit a rectangular dual. Algorithms that introduce edges and vertices into the given graph until a rectangular dual can be constructed are also presented. >