Reconfiguration Unit Research Articles

Calculation and Optimization of the Wheel-Track Mobile Robot Reconfi guration Mechanism

The actual problem of an autonomous transport robot design for work in an unstructured environment and in emergency situations is considered. The design of the robot contains a combined system, consisting of transformable track and wheel groups, which allows moving over different types of surfaces, including the conditions of the urban environment, in particular flights of stairs. Movement on a flat surface is carried out only by wheel groups with raised track groups, which provides an increased speed of the robot. Movement on uneven surface is carried out only by track groups, while the wheel groups are raised. It provides increased cross-country ability. Staircase and complex obstacles can be overcome with the simultaneous use of wheel and track groups at angle of the wheel groups relative to the track groups during reconfiguration of geometric shapes and steps of the staircase and obstacles. The robot reconfiguration unit is made in the form of a lever mechanism with electric cylinders, which can be self-locking. It implements the switching of the robot movement modes, as well as lifting the wheel group to the required angle for overcoming obstacles. The analysis of the design and calculation of the lever mechanism of the wheel-track robot is carried out. A kinematic model of the reconfiguration unit has been developed. Relationships between the angles and length of the levers, as well as between the angular velocity of movement of the levers and the speed of movement of the electric cylinder pusher of the lever mechanism are obtained. Optimization of the reconfiguration block operation by creating its mathematical model for programming in the Matlab package is done. The target function and restrictions on the system operation have been determined. As a result, improved mechanical characteristics of the reconstruction unit are obtained.

Single-Phase Voltage Source Multi-Level Inverter Hysteresis SVPWM Reconfigurable Fault-Tolerant Control Method

A hysteresis space vector pulse width modulation (SVPWM) reconfigurable fault-tolerant method for single-phase voltage source multi-level inverter with current tracking is proposed. Firstly, the influence of single switch open circuit fault and double switches open circuit fault on the voltage vector of the inverter is analyzed, and on this basis, the equivalent replacement of the voltage vector is obtained by using the topology reconstruction of the inverter, and the redundant voltage vectors with overlapping positions are preferred for equivalent replacement. If there are no coincident non-fault vectors, the other non-fault vectors with the closest position and effect are selected. The fault-tolerant method does not need the switching operation between the main power switching device and spare power switching device of the inverter, and can directly control the on–off process of the inverter reconfiguration unit through the driving signal of insulated gate bipolar translator (IGBT), which is simple and stable. Under the conditions of single switch open circuit and most double switches open circuit, the output current of the inverter can accurately track the reference current.

Robust Adaptive Control Allocation Schemes for Overactuated Underwater Vehicles under Actuator Faults

In this paper, we investigate the fault-tolerant path following control problem for an overactuated underwater vehicle subject to input saturation and rate of change constraints, actuator faults and parametric (mass and inertia) uncertainty. A robust adaptive control allocation strategy is proposed capable to reconfigure the distribution of the control effort among the remaining healthy actuators in the case some of them failed. The online estimation of actuators' effectiveness and bias fault parameters is integrated with the control allocation and reconfiguration unit. The robustness and performance of the scheme are shown by evaluating the results of simulations and pool experiments of different path-following control problems using overactuated underwater vehicles.

CNN-Based Intelligent Fault-Tolerant Control Design for Turbofan Engines With Actuator Faults

In this paper, the problem of fault-tolerant control is investigated for turbofan engines with actuator faults. The controller involvement has repressed the effects of actuator faults on the controlled outputs of turbofan engines, making fault-tolerant control difficult. To solve this problem, the internal gas-path data of turbofan engines is introduced to provide conducive fault information. Besides, the useful property of the convolution neural network (CNN) is explored and utilized in fault-tolerant control. Based on the analysis of actuator faults, by using the Lyapunov stability and $L_{2}$ -gain like theorems, a novel CNN-based intelligent fault-tolerant control system for turbofan engines is proposed, including a CNN-based fault diagnosis module and a nonlinear fault-tolerant control with corresponding reconfiguration unit. The CNN-based intelligent fault-tolerant control system has the advantages of reducing the accuracy requirements of the mathematical description of turbofan engines. Furthermore, the proposed system can diagnose actuator faults and reduce the adverse effects of actuator faults on turbofan engines. Finally, simulation results are presented to demonstrate the efficiency of the designed method.

A metaphor-less based AI technique for optimal deployment of DG and DSTATCOM considering reconfiguration in the RDS for Techno-Economic benefits

The advent of distributed energy resources is undoubtedly transforming the nature of the electric power system. The crisis of conventional energy sources and their environmental effects resulted in the integration of Distributed Generators (DGs) into the distribution system. Simultaneous application of optimum network reconfiguration, DGs, and Distribution Static Compensator (DSTATCOM) unit’s placement in the Radial Distribution Systems (RDS) comes with a raft of technical, economic, and environmental benefits. Benefits include improved power quality, reliability, stability, mitigation of power losses, and voltage profile improvement. In this paper, the combinational process of optimal deployment of DGs and DSTATCOM units in RDS with suitable network reconfiguration to achieve positive benefits has been analyzed. A recent metaphor-less based Artificial Intelligence (AI) technique named the Rao-1 method is employed to overcome this combinational nonlinear optimization problem. The objective functions are to mitigate the power losses, enhance the voltage profile, and voltage stability index of the RDS considering the net economic cost-benefit to the distribution utility. The simulation study of this pragmatic approach problem is carried out on IEEE 33-bus RDS. The comparison of the results obtained by the Rao-1 method with other existing meta-heuristic optimization methods has been made to show its efficacy.

Fault-tolerant cooperative control of networked discrete-event systems

Abstract Networked discrete-event systems like smart manufacturing systems consist of subsystems, which are physically coupled and digitally connected by a communication network. The subsystems are able to solve their local tasks autonomously and to cooperate with another subsystem if necessary. In the second situation, the network units of both subsystems initiate the cooperation via the communication network. The flexibility of the subsystems to solve autonomous and cooperative tasks demonstrates an important property that is required for manufacturing systems in Industry 4.0. The paper concerns the situation that a fault occurs within a subsystem, which has to be detected and the controller has to be adapted. To this aim, the subsystems are extended by a diagnostic unit and a reconfiguration unit. The diagnostic unit detects and identifies the fault, whereas the reconfiguration unit applies a locally reconfigured controller. It is shown that if the fault has the property to be networked reconfigurable, the fault is locally reconfigurable without affecting the overall system.

Reconfigurable fault tolerant routing for networks-on-chip with logical hierarchy

This paper presents a reconfigurable fault tolerant routing for Networks-on-Chip organized into hierarchical units. In case of link faults or failure of switches, the proposed approach enables the online adaptation of routing locally within each unit while deadlock freedom is globally ensured in the network. Experimental results of our approach for a 16 × 16 network show a speedup by a factor of almost four for routing reconfiguration compared to the state-of-the-art approach. Evaluation with transient faults shows that a dedicated reconfiguration unit enables successful reconfiguration of routing tables even in case of high error probabilities.

Actuator Fault Tolerant Control: A Receding Horizon Set-Theoretic Approach

In this note, a novel actuator Fault Tolerant Control strategy for constrained discrete time linear systems subject to bounded disturbances is proposed. The scheme consists of three modules: a bank of estimators, each one associated with healthy and faulty model configurations, a logic mechanism for identifying healthy-to-faulty and faulty-to-healthy transitions and an estimate based control reconfiguration unit. The idea is to abstractly describe healthy and faulty plant configurations by means of a switching paradigm and sequences of pre-computed inner approximations of one-step controllable sets. Such regions are then on-line exploited together with a switching logic to determine the current plant configuration on the basis of the state estimate provided by the observers.

Improving instruction level parallelism through reconfigurable units in superscalar processors

With reducing feature sizes, more transistors can be integrated on the chip. The increased transistor budget can be utilized to improve the instruction level parallelism (ILP) exploited from the processor. However, the transistors cannot be used to arbitrarily increase the processor width and size in the hope of exploiting better ILP. In this paper, we propose an architecture where the superscalar datapath is tightly coupled with a reconfigurable unit (RFU). The reconfiguration unit is configured to execute the traces of dynamic instructions that are frequently executed. To address the data dependency issues between the instructions in the superscalar and the RFU, we propose to execute the trace on the RFU with predicted values. When the trace instructions reach the issue queue in the superscalar, the predictions are validated. In this technique, performance improvement is obtained for correct prediction, whereas no performance degradation is incurred for mispredictions. With this architecture, we observe an average instructions per cycle (IPC) improvement of about 11% over the simulated SPEC 2000 benchmarks, using a very small last value data value predictor.

Reconfiguration Heuristics for Logical Topologies in Wide-Area WDM Networks

Wavelength division multiplexing (WDM) technology offers the capability of building wide-area networks with high speed. Reconfigurability is a key feature of a WDM network that enables the network logical topology to change dynamically in response to the changing traffic patterns. There are two important issues involved in the reconfiguration of a network logical topology. One is how to determine the new logical topology corresponding to the current topology. It needs to consider a trade-off between the performance of the new target topology and the cost of the topology transition from the current topology to the new one. The other is how to determine the transition sequence from the current topology to the new one. It needs to control the disruption to the network as less as possible during the reconfiguration process. In this paper, we focus on the latter problem and propose several heuristic algorithms that reconfigure logical topologies in wide-area wavelength-routed optical networks. Our reconfiguration algorithms attempt to control the disruption to the network as less as possible during the reconfiguration process. For this purpose, a lightpath is taken as the minimum reconfiguration unit. The proposed algorithms are evaluated by using an NFSNET-like network model with 16 nodes and 25 links. The results show that very simple algorithms provide very small computational complexity but poor performance, i.e., large network disruption, and that an efficient algorithm provides reasonable computational complexity and very good performance. More complex algorithms may improve performance somewhat further but have unrealistically large computational complexity.

A built-in self-repair design for RAMs with 2-D redundancy

This brief presents a built-in self-repair (BISR) scheme for semiconductor memories with two-dimensional (2-D) redundancy structures, i.e., spare rows and spare columns. The BISR design is composed of a built-in self-test module and a built-in redundancy analysis (BIRA) module. The BIRA module executes the proposed RA algorithm for RAM with a 2-D redundancy structure. The BIRA module also serves as the reconfiguration unit in the normal mode. Experimental results show that a high repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories) is achieved with the BISR scheme. The BISR circuit has a low area overhead-about 4.6% for an 8 K /spl times/ 64 SRAM.

A vehicle electric power generation system with improved output power and efficiency

This paper presents a vehicle electric power generation system with improved output and efficiency. At low speed, the output power of the system is maximized by using a controllable rectifier to optimize the operating conditions of the alternator. The controllable rectifier is synchronized with the alternator based on the zero-crossing information of the third harmonic voltage. The output power is controlled by shifting the phase voltage with respect to the third harmonic voltage. At high speed, the system output power and efficiency are increased by changing the number of turns of the alternator stator windings. Winding reconfiguration is realized by winding taps and use of two rectifiers and two switches. A proof-of-concept system has been built and tested in the laboratory. The test data show that the new system can increase the output power significantly at both low and high speed. In the present range in which the alternator is operated most of the time, the winding reconfiguration increases both the output power and efficiency. For the same output power as a production alternator, the winding reconfiguration unit improves the efficiency by 21% (from 47% up to 57%).