Reconfiguration Time Overhead Research Articles

An Efficient On-Demand Hardware Replacement Platform for Metamorphic Functional Processing in Edge-Centric IoT Applications

The paradigm of Internet-of-things (IoT) systems is changing from a cloud-based system to an edge-based system. These changes were able to solve the delay caused by the rapid concentration of data in the communication network, the delay caused by the lack of server computing capacity, and the security issues that occur in the data communication process. However, edge-based IoT systems performance was insufficient to process large numbers of data due to limited power supply, fixed hardware functions, and limited hardware resources. To improve their performance, application-specific hardware can be installed in edge devices, but performance cannot be improved except for specific applications due to a fixed function of an application-specific hardware. This paper introduces an edge-centric metamorphic IoT (mIoT) platform that can use various hardware modules through on-demand partial reconfiguration, despite the limited hardware resources of edge devices. In addition, this paper introduces an RISC-V based metamorphic IoT processor (mIoTP) with reconfigurable peripheral modules. We experimented to prove that the proposed structure can reduce the server access of edges and can be applied to a large-scale IoT system. Experiments were conducted in a single-edge environment and a large-scale environment combining one physical edge and 99 virtual edges. According to the experimental results, the edge-centric mIoT platform that executes the reconfiguration prediction algorithm at the edge was able to reduce the number of server accesses by up to 82.2% compared to our previous study in which the prediction process was executed at the server. Furthermore, we confirmed that there is no additional reconfiguration time overhead even for the large IoT systems.

VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC

Hybrid architectures integrating a processor with an SRAM-based FPGA fabric—for example, Xilinx ZynQ SoC—are increasingly being used as a single-chip solution in several market segments to replace multi-chip designs. These devices not only provide advantages in terms of logic density, cost and integration, but also provide run-time in-field reconfiguration capabilities. However, the current reconfiguration capabilities provided by vendor tools are limited to the module level. Therefore, incremental run-time configuration memory changes require a lengthy compilation time for off-line bitstream generation along with storage and reconfiguration time overheads with traditional vendor methodologies. In this paper, an internal configuration access port (ICAP) controller that provides a versatile fine-grain resource-level incremental reconfiguration of the programmable logic (PL) resources in ZynQ SoC is presented. The proposed controller implemented in PL, called VR-ZyCAP, can reconfigure look-up tables (LUTs) and Flip-Flops (FF). The run-time reconfiguration of FF is achieved through a reset after reconfiguration (RAR)-featured partial bitstream to avoid the unintended state corruption of other memory elements. Along with versatility, our proposed controller improves the reconfiguration time by 30 times for FFs compared to state-of-the-art works while achieving a nearly 400-fold increase in speed for LUTs when compared to vendor-supported software approaches. In addition, it achieves competitive resource utilization when compared to existing approaches.

Multiobjective Optimization Approach for a Portable Development of Reconfigurable Real-Time Systems: From Specification to Implementation

This paper deals with the reconfigurable real-time systems that should be adapted to their environment under real-time constraints. The reconfiguration allows moving from one implementation to another by adding/removing/modifying parameters of real-time software tasks which should meet related deadlines. Implementing those systems as threads generates a complex system code due to the large number of threads, which may lead to a reconfiguration time overhead as well as the energy consumption and the memory allocation increase. Thus this paper proposes a multiobjective optimization approach for reconfigurable systems called MO2R2S for the development of a reconfigurable real-time system. Given a specification, the proposed approach aims to produce an optimal design while ensuring the system feasibility. We focus on three optimization criteria: 1) response time; 2) memory allocation; and 3) energy consumption. To address the portability issue, the optimal design is then transformed to an abstract code that may in turn be transformed to a concrete code which is specific to a procedural programming (i.e., POSIX) or an object-oriented language (i.e., RT-Java). The MO2R2S approach allows reducing the number of threads by minimizing the redundancy between the implementation sets. By an experimental study, such optimization permits to decrease the memory allocation by 28.89%, the energy consumption by 40.2%, and the response time by 61.32%.

NoC-DPR: A new simulation tool exploiting the Dynamic Partial Reconfiguration (DPR) on Network-on-Chip (NoC) based FPGA

Due to the ability of Dynamic Partial Reconfiguration (DPR) of SRAM-based Field Programmable Gate Arrays (FPGAs) to add more flexibility over runtime phase, DPR is attracting more interest. Recently, FPGA manufacturers are facilitating the design of applications that utilize DPR. One of the main issues in our knowledge of DPR's current techniques (i.e., ICAP and JTAG) is a performance bottleneck; only one DPR is allowed at a time. In this paper, a state-of-art NoC-based FPGA simulator which supports DPR simulation is proposed. The proposed NoC-DPR simulator is used to investigate design limitations and performance degradation of using DPR on NoC-based FPGA. To estimate the reconfiguration time overhead, which results from increasing the number of simultaneous DPRs on FPGA fabric, some experimental investigations are carried out using NoC-DPR simulator. These investigations revealed that the overhead of reconfiguration time increases exponentially with increasing the number of simultaneous DPRs. However, further investigations show that the network of wormhole routers with virtual channels optimizes the reconfiguration time with a factor up to 4x than that of the network of wormhole routers without virtual channels.

Extended overlay architectures for heterogeneous FPGA cluster management

This paper proposes a novel approach for the hardware virtualization of FPGA resources, based on overlay architectures. Overlays are reconfigurable architectures synthesized on top of commercial-of-the-shelf (COTS) FPGAs. They have demonstrated to improve portability, speed up reconfiguration, and promote resource abstraction hence durability. This work demonstrates how slightly extending the architecture overlaying on top of COTS FPGAs can bring novel features for sake of improved management of hardware tasks, and ensure the binary compatibility among heterogeneous FPGAs. This comes along with a deployment platform and a software stack offering an operating system service. As a result, the platform is capable of node-to-node a hardware application live migration, while operating a cluster of heterogeneous FPGAs. Besides, the proposed software stack ensures backward compatibility when introducing a new overlay architecture. This paper also introduces accurate cost models for the early estimation of the reconfiguration time overhead. This approach that has been demonstrated in DASIP international conference is evaluated in this paper on both the Xilinx Artix-7 and Altera Cyclone V C9 FPGAs.

Development of the reconfiguration acceleration method in the dynamically reconfigurable computing systems

The problem of performance improvement of reconfigurable computing systems, including solving the problem of reconfiguration overhead reduction was considered. A new reconfiguration acceleration method and hardware for its implementation, which allow to minimize the reconfiguration time overhead were proposed. Analytical expressions that formalize the reconfiguration acceleration method, justify the virtually complete removal of unproductive reconfiguration time by reducing the communication component of time that provides an intensive reconfiguration acceleration were obtained. The formalization shows that the volume of the removed unproductive time component is linearly dependent on the number of repetitive tasks. Thus, using the proposed method is the most efficient in the algorithms that contain a large number of similar tasks. The proposed hardware for schedule management of placement and support of configurations of functional units, based on the multi-level memory, provide effective support of the reconfiguration overhead reduction method and allow to reduce computational complexity of reconfiguration control algorithms and solve the problem of limited resources of internal memory of the FPGA. The designed emulator of the reconfigurable computing system and software model of the reconfiguration acceleration method enable the real-time control simulation of reconfigurable resources. The developed software is a handy tool to study the temporal characteristics of the reconfigurable computing system. Simulation of the reconfiguration acceleration method for computing algorithms with the multilevel structure, which is experimentally confirmed by theoretical research was performed.

Reconfiguration time overhead on field programmable gate arrays: reduction and cost model

Partial reconfiguration suffers from low performance and thus its use is limited when the reconfiguration overhead is too high compared to the task execution time. To overcome this issue, the authors present a fast internal configuration access port (ICAP) controller, FaRM, providing high-speed configuration and easy-to-use readback capabilities, reducing configuration overhead as much as possible. In order to enhance performance, FaRM uses techniques such as master accesses, ICAP overclocking, bitstream pre-load into a controller and bitstream compression technique, Offset-run length encoding (RLE), which is an improvement of the RLE algorithm. Combining these approaches allows us to achieve an ICAP theoretical throughput of 800 MB/S at 200 MHz. In order to complete our approach, we provide a cost model for the reconfiguration overhead for the system level that can be used during the early stages of development. The authors tested their approach on an Advanced Encryption Standard AES encryption/decryption architecture.

A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback

Dynamically reconfigurable computing platforms provide promising methods for dynamic management of hardware resources, power, and performance. Yet, progress in dynamically reconfigurable computing is fundamentally limited by the reconfiguration time overhead. Prior research in the development of dynamic partial reconfiguration (DPR) controllers has been limited by its use of the Processor Local Bus (PLB). As a result, the bus was unavailable during DPR. This resulted in significant time overhead. To minimize the overhead, we introduce the use of a multiport memory controller (MPMC) that frees the PLB during the reconfiguration process. The processor is thus allowed to switch to other tasks during the reconfiguration operation. This effectively limits the reconfiguration overhead. An interrupt is used to inform the processor when the operation is complete. Therefore, the system can multitask during the reconfiguration operation. Furthermore, to maximize performance, we introduce the use of overclocking with active feedback. During overclocking, the use of active feedback is used to ensure that the device voltage and temperature are within nominal operating conditions. All of these contributions lead to significant performance improvements over current partial reconfiguration subsystems. The portability of the system, demonstrated on the Virtex-4 and the Virtex-5, consists of four different hardware platforms.

Dynamic reconfiguration architectures for multi-context FPGAs

Field-programmable gate arrays (FPGAs) are being integrated with processors on the same motherboard or even chip in order to achieve flexible high-performance computing, and this may become main stream in chip multi-core architectures. However, the expensive FPGA area is often used inefficiently, with much of the logic idle at any given time. This work, motivated by the Dynamic-Link Library (DLL) concept in software, explores the possibility of “hardware DLLs” by finding ways for fast dynamic incremental reconfiguration of FPGAs. So doing would, among other things, enable same-function replication at any given time, with functions changing quickly over time, thereby enabling efficient exploitation of data parallelism at no additional hardware cost. We present two new multi-context FPGA architectures based on two different configuration storage architectures: local and centralized. Problems such as configuration storage and reconfiguration (time, power and space) overhead are considered. Well known area and power models are used in evaluating various approaches and in order to provide guidelines for matching architectures to target applications. Lastly, we provide insights into resulting scheduling issues. Our findings provide the foundation and “rules of the game” for subsequent development of reconfiguration schedulers and execution environments.

An EDF schedulability test for periodic tasks on reconfigurable hardware devices

In this paper, we consider the scheduling of periodic real-time tasks on reconfigurable hardware devices. Such devices can execute several tasks in parallel. All executing tasks share the hardware resource, which makes the scheduling problem differ from single- and multiprocessor scheduling. We adapt the global EDF multiprocessor scheduling approach to the reconfigurable hardware execution model and define two preemptive scheduling algorithms, EDF-First-k-Fit and EDF-Next-Fit . For these algorithms, we present a novel linear-time schedulability test and give a proof based on a resource augmentation technique. Then, we propose a task placement and relocation scheme utilizing partial device reconfiguration. This scheme allows us to extend the schedulability test to include reconfiguration time overheads. Experiments with synthetic workloads compare the scheduling test with the actual scheduling performance of EDF-First-k-Fit and EDF-Next-Fit . The main evaluation result is that the reconfiguration overhead is acceptable if the task computation times are one order of magnitude higher than the device reconfiguration time.