Reconfigurable Ring Oscillator Research Articles

Frequency-Controlled Fluidic Oscillators for Soft Robots.

Electronic-free controls have recently emerged as one of the main topics in soft robotics. However, electronic-free fluidic circuits still lack controllability and reconfigurability to achieve different functions. Here, reconfigurable pneumatic valves that widen the design space of fluidic circuits are presented. The significance of two parameters on the valve's operation: a pre-defined manufacturing parameter that sets the initial operational range of the valve, and a second, on-the-fly modifiable geometric parameter that shifts the behavior of the valve during operation is shown. It is demonstrated that equipping the valve with these reconfigurable features enables the tuning of fluidic oscillatory circuits as illustrated by two examples: a frequency-controlled relaxation oscillator and a reconfigurable ring oscillator. The relaxation oscillator is employed to control the actuation frequency of a soft hopper, which is able to achieve 80 to 125 hops min-1 and a hopping speed ranging from ≈1 to ≈1.185 BL s-1. Additionally, the reconfigurable ring oscillator is used to demonstrate how each output frequency can be controlled independently, via a soft robotic crawler that can navigate in three directions, and a volume-controlled fluidic pump able to achieve mixing of solutions in environments where electronic components cannotoperate.

On-chip static and dynamic monitors for low power applications

Due to the increasing demand for battery-operated mobile devices in the market, low power consumption inside the chip is an essential ingredient during the chip design. Static and dynamic monitors are needed to achieve low power in modern chips. The static or process monitor provides information about global and local process variation inside the chip. The dynamic or in situ monitor provides information about the global, local, and environmental variation on the critical path of the design inside the chip. In this work, a static monitor is discussed using a reconfigurable ring oscillator which extracts the threshold voltage information. A dynamic monitor using warning flip-flop is discussed which can be used for dynamic voltage and frequency scaling to achieve low power consumption. Both static and dynamic monitors are experimentally validated in a test chip, that is implemented in CMOS 130 nm technology node.

On-Chip Threshold Voltage Variability Estimation Using Reconfigurable Ring Oscillator

Process variability is one of the major concerns in semiconductor manufacturing in advanced technology nodes. This paper explains an all-digital technique to estimate the impact of threshold voltage ( ${V}_{\text{th}}$ ) of NMOS device under test (NDUT) using a reconfigurable ring oscillator (RRO) which consists of a chain of threshold voltage measurement cell (TVMC). The difference of periods of RRO due to two voltage levels, i.e., ${V}_{\text {dd}}$ and ( ${V}_{\text {dd}}-{V}_{\text {th}}$ ) at the intermediate node provides information about the impact of threshold voltage of an NDUT. A lognormal model is developed to extract the threshold voltage information from the RRO period difference. The maximum difference in predicting the threshold voltage from the proposed model and through SPICE simulation is found to be less than 1.5%. Measured results from 26 test chips in 130-nm process show the feasibility of estimating the $ {V}_{\text {th}}$ variability from the proposed RRO test structure. The proposed test circuit with 300 samples of NDUT occupies a silicon area of ${280} \,\, {\times }\,\, {64}\,\, {\mu } \text {m}^{{2}}$ .

XOR-Based Low-Cost Reconfigurable PUFs for IoT Security

With the rapid development of the Internet of Things (IoT), security has attracted considerable interest. Conventional security solutions that have been proposed for the Internet based on classical cryptography cannot be applied to IoT nodes as they are typically resource-constrained. A physical unclonable function (PUF) is a hardware-based security primitive and can be used to generate a key online or uniquely identify an integrated circuit (IC) by extracting its internal random differences using so-called challenge-response pairs (CRPs). It is regarded as a promising low-cost solution for IoT security. A logic reconfigurable PUF (RPUF) is highly efficient in terms of hardware cost. This article first presents a new classification for RPUFs, namely circuit-based RPUF (C-RPUF) and algorithm-based RPUF (A-RPUF); two Exclusive OR (XOR)-based RPUF circuits (an XOR-based reconfigurable bistable ring PUF (XRBR PUF) and an XOR-based reconfigurable ring oscillator PUF (XRRO PUF)) are proposed. Both the XRBR and XRRO PUFs are implemented on Xilinx Spartan-6 field-programmable gate arrays (FPGAs). The implementation results are compared with previous PUF designs and show good uniqueness and reliability. Compared to conventional PUF designs, the most significant advantage of the proposed designs is that they are highly efficient in terms of hardware cost. Moreover, the XRRO PUF is the most efficient design when compared with previous RPUFs. Also, both the proposed XRRO and XRBR PUFs require only 12.5% of the hardware resources of previous bitstable ring PUFs and reconfigurable RO PUFs, respectively, to generate a 1-bit response. This confirms that the proposed XRBR and XRRO PUFs are very efficient designs with good uniqueness and reliability.

Accurate Shielded Interconnect Delay Estimation by Reconfigurable Ring Oscillator

Shielding, which is used in VLSI designs to prevent noise interference from the cross-coupling capacitance between adjacent signals can also be used to tune the propagation delay of the clock signals in designs operating at low GHz frequencies. This paper presents a detailed design for a 16-nm ring oscillator with built-in reconfigurable shielding, and a delay estimation methodology. Together these provide a post-silicon measurement methodology that can derive accurate shielding delays without any direct delay measurements. The shielded ring oscillator and the testing methodology are designed to minimize the effects of on-die variations on estimation accuracy. Comparisons of the estimated delays with SPICE simulations show very good fit across process technology corners. The circuit was fabricated in 16-nm technology. The accuracy and robustness of the estimation methodology were verified by cross-validation, obtained from both pre and post-silicon measurements.

A temperature monitor circuit with small voltage sensitivity using a topology-reconfigurable ring oscillator

In this paper, we propose a temperature monitor circuit that exhibits a small supply voltage sensitivity adopting a circuit topology of a reconfigurable ring oscillator. The circuit topology of the monitor is crafted such that the oscillation frequency is determined by the amount of subthreshold leakage current, which has an exponential dependence on temperature. Another important characteristic of the monitor is its small supply voltage sensitivity. The measured oscillation frequency of a test chip fabricated in a 65 nm CMOS process varies only 2.6% under a wide range of supply voltages from 0.4 to 1.0 V at room temperature. The temperature estimation error ranges from −0.3 to 0.4 °C over a temperature range of 10 to 100 °C.

Area-efficient reconfigurable ring oscillator for device and circuit level characterization of static and dynamic variations

Accurate characterization of transistor variation under dynamic switching condition has become important for reliable digital circuit design. This paper proposes a reconfigurable ring oscillator (RO) structure which enables measurement of transistor level variation. Each inverter stage in the RO can be configured into several delay modes. The delay of a particular inverting stage can be made dominant by configuring an inhomogeneous RO structure. By scanning the inhomogeneous stage, delay variation of each stage can be measured. Furthermore, pMOSFET and nMOSFET variation can be measured separately by making only rise or fall delay dominant. Specific transistor with random telegraph noise (RTN) in the inhomogeneous stage can be identified by reconfiguring the inhomogeneous stage. Thus, using a single RO, static delay variation as well as dynamic variation such as RTN can be measured. The area for a 127-staged reconfigurable RO including peripheral circuits is only 0.0085 mm2 thus area-efficient measurement becomes possible. Measurement results from a 65-nm test chip shows the validity of the proposed circuit structure.

On-Chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring Oscillator

In this brief, a new technique to measure the on-chip rise/fall delay of an individual gate is presented. In the proposed technique, the rise/fall gate delay is measured using the duty cycle of a reconfigurable ring oscillator (RRO). A set of linear equations is formed with the different configuration settings of the RRO, relating the rise/fall delay of all the gates in the path of the RRO to the positive/negative duty cycle of the undivided RRO. The high-frequency undivided RRO signal is needed for this type of measurement as it preserves the rise/fall delay of an individual gate. However, it is difficult to bring the high-frequency undivided RRO signal outside the chip due to the frequency limitation of the output pad. The high-frequency RRO signal is subsampled by a clock that is generated from an on-chip phase-locked loop to make it low frequency. The rise and fall delays of an individual gate can be calculated from the difference of the duty cycle of the subsampled RRO signal at two different configurations of the RRO. The proposed concept is validated in a test chip that is fabricated in an industrial 65-nm technology node.

Area-efficient reconfigurable-array-based oscillator for standard cell characterisation

Today's multi-million digital integrated circuit design highly depends on the quality of the standard cell library. In this study, an all-digital reconfigurable-array-based test structure is presented to test the quality (i.e. functionality and performance) of all types of logic gates in the standard cell library using the reconfigurable array of gate delay measurement cell. The gate delay is estimated using the least squares method with measured reconfigurable ring oscillator's (RO) period/frequency. As the least squares method averages out the random noise in the measured RO period, measured gate delay is estimated accurately. The reconfigurable-array structure can easily isolate a faulty standard cell from a non-faulty standard cell. The test structure is area efficient with a saving of 1.6× and 2× area compared with the normal RO-based delay measurement in 180 nm and 65 nm technology node, respectively. A subset of standard cells is tested using this reconfigurable-array structure. A test chip has been fabricated in an industrial 180 nm technology node to study the feasibility of the approach. The measured results from 20 chips are reported to show the amount of within-die and die-to-die variation.

Analysis of Within-Die Complementary Metal–Oxide–Semiconductor Process Variation with Reconfigurable Ring Oscillator Arrays Using HiSIM

Process-related variations are becoming a major concern for complementary metal–oxide–semiconductor (CMOS) technologies as the transistor size is scaled down. Hence, it is necessary to characterize the within-die (WID) and die-to-die (D2D) variations to establish a design methodology for the correct operation of ICs in the presence of such variations. Here, we have analyzed the stage-delay variation in ring oscillator arrays, fabricated in 180 nm CMOS technology, with large stage numbers and the possibility of flexible replacement for all ring oscillator stages. These allow an experimental analysis of the two-dimensional (2D) properties of the WID variation over the 1.69×1.59 mm2 area covered by the ring oscillators. Our results show that the measured variation data over this large area is still mainly of a Gaussian nature. Simulation of the delay stages of these ring oscillator arrays using the compact Hiroshima University STARC (Semiconductor Technology Academic Research Center) insulated gate field effect transistor (IGFET) Model (HiSIM) and some of the measurement data suggest that a systematic variation component, which does not change the Gaussian nature of the overall measurement data, may be present in the vertical direction of the ring oscillator array.

Analysis of Within-Die Complementary Metal–Oxide–Semiconductor Process Variation with Reconfigurable Ring Oscillator Arrays Using HiSIM

Process-related variations are becoming a major concern for complementary metal–oxide–semiconductor (CMOS) technologies as the transistor size is scaled down. Hence, it is necessary to characterize the within-die (WID) and die-to-die (D2D) variations to establish a design methodology for the correct operation of ICs in the presence of such variations. Here, we have analyzed the stage-delay variation in ring oscillator arrays, fabricated in 180 nm CMOS technology, with large stage numbers and the possibility of flexible replacement for all ring oscillator stages. These allow an experimental analysis of the two-dimensional (2D) properties of the WID variation over the 1.69×1.59 mm2 area covered by the ring oscillators. Our results show that the measured variation data over this large area is still mainly of a Gaussian nature. Simulation of the delay stages of these ring oscillator arrays using the compact Hiroshima University STARC (Semiconductor Technology Academic Research Center) insulated gate field effect transistor (IGFET) Model (HiSIM) and some of the measurement data suggest that a systematic variation component, which does not change the Gaussian nature of the overall measurement data, may be present in the vertical direction of the ring oscillator array.

Within-Die Gate Delay Variability Measurement Using Reconfigurable Ring Oscillator

We report the design and characterization of a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and noninverting) in its unmodified form. The test circuit comprises of digitally reconfigurable ring oscillator (RO). The gate under test is embedded in each stage of the ring oscillator. A system of linear equations is then formed with different configuration settings of the RO, relating the individual gate delay to the measured period of the RO, whose solution gives the delay of the individual gates. Experimental results from a test chip in 65-nm process node show the feasibility of measuring the delay of an individual inverter to within 1 ps accuracy. Delay measurements of different nominally identical inverters in close physical proximity show variations of up to 28% indicating the large impact of local variations. As a demonstration of this technique, we have studied delay variation with poly-pitch, length of diffusion (LOD) and different orientations of layout in silicon. The proposed technique is quite suitable for early process characterization, monitoring mature process in manufacturing and correlating model-to-hardware.

A proposed method for dynamic fitting of MOS model parameters

A method for optimization of MOS model parameters is introduced. The method is based upon dynamically fitting the measured frequency response of a reconfigurable ring oscillator. The ring oscillator contains two added switching transistors and two loading capacitors. By controlling the switching transistors, the capacitive load of the inverters and thus the oscillation frequency can be varied. The simulated and the measured frequencies are compared and the derived average error is minimized. Sequential iterations using combined mathematical methods are applied to the procedure. Simplifications are introduced in order to shorten the computational time. The effectiveness of the method on improving the accuracy of simulation is demonstrated with numerical examples.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>