Reconfigurable Physical Unclonable Functions Research Articles

Reconfigurable Physically Unclonable Functions Based on Nanoscale Voltage‐Controlled Magnetic Tunnel Junctions

AbstractWith the fast growth of the number of electronic devices on the internet of things (IoT), hardware‐based security primitives such as physically unclonable functions (PUFs) have emerged to overcome the shortcomings of conventional software‐based cryptographic technology. Existing PUFs exploit manufacturing process variations in a semiconductor foundry technology. This results in a static challenge–response behavior, which can present a long‐term security risk. This study shows a reconfigurable PUF based on nanoscale magnetic tunnel junction (MTJ) arrays that uses stochastic dynamics induced by voltage‐controlled magnetic anisotropy (VCMA) for true random bit generation. A total of 100 PUF instances are implemented using 10 ns voltage pulses on a single chip with a 10 × 10 MTJ array. The unipolar nature of the VCMA mechanism is exploited to stabilize the MTJ state and eliminate bit errors during readout. All PUF instances show entropy close to one, inter‐Hamming distance close to 50%, and no bit errors in 104 repeated readout measurements.

Purely Electrical Controllable Spin–Orbit Torque‐Based Reconfigurable Physically Unclonable Functions

AbstractIn the field of information hardware security, random variations obtained during device manufacturing process play a key role in generating unique and unclonable security keys. Existing physical unclonable functions (PUFs) utilizing these static randomnesses usually exhibit static challenge‐response pairs, which cannot be refreshed and limit their application prospects. Here, it is demonstrated that purely electrical controllable spin–orbit torque (SOT)‐based reconfigurable PUFs (rPUFs) can be realized in Pt/IrMn/Co/Ru/CoPt heterojunctions. By applying current pulses along two orthogonal directions, both the exchange bias between IrMn and Co and the SOT switching polarity (clockwise or counterclockwise) of perpendicularly magnetized CoPt can be reversibly controlled, which enables the realization of four rPUF states within a single device. By taking advantages of the sample growth and micro‐nanofabrication induced variations in the critical switching current density of SOT‐driven magnetization switching, the rPUF device with relatively good uniqueness and low bit error rate is achieved. Our work provides an approach to information hardware security and broadens the application of spintronics.

A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs

As a lightweight hardware security primitive, physical unclonable functions (PUFs) can provide reliable identity authentication for devices of Internet of Things (IoTs) with limited resources. However, the delay-based PUF structures in authentication protocols have static responding behaviors, which make them vulnerable to modeling attacks. To address this issue, many complex PUF designs have been designed to increase the nonlinearity of their models. However, most of them can still be broken by modeling-based machine learning (ML) attacks. In this article, a dynamic responding mechanism for PUF designs to generate dynamic responses is proposed. Different from the concept of logically reconfigurable PUFs, the proposed mechanism does not rely on external inputs to provide reconfiguration signals. And different from the conventional PUF authentication protocols that use large-size linear feedback shift register (LFSR) to extend the master challenge, the proposed scheme uses internally generated dynamic signals to obfuscate the master challenge to generate multiple subchallenges. These subchallenges are then input to the underlying strong PUF to generate multibit dynamic responses. It can prevent an attacker from obtaining valid challenge-response pairs (CRPs) for the underlying PUF. A security authentication protocol is also proposed, the special authentication bit-string design can resist both conventional ML attacks and the latest covariance matrix adaptation evolution strategies (CMA-ES) variant.

STT-MRAM-Based Reliable Weak PUF

In recent years, micro-nano device characteristics like ferroelectrics and resistive switching are being used to build important security primitives such as Physical Unclonable Function (PUF). The micro-nano device-based hardware security primitives, although with higher security, energy efficiency, and integration density, suffer from serious reliability issues caused by process scaling. To mitigate this issue, this paper introduces a reconfigurable weak PUF based on spin-transfer torque magnetoresistive random-access memory (STT-MRAM), which adopts the crossing switches implemented with simple demultiplexes (DEMUXs) to improve the flexibility and reliability. Moreover, two algorithms, <monospace>neighboring bit lines</monospace> and <monospace>top-<inline-formula><tex-math notation="LaTeX">$n$</tex-math><alternatives><mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>n</mml:mi></mml:math><inline-graphic xlink:href="hu-ieq1-3095657.gif" xmlns:xlink="http://www.w3.org/1999/xlink"/></alternatives></inline-formula></monospace> , are proposed to enlarge the gap between two parallel reading currents, thus further enhancing the reliability of PUF responses. Experimental results demonstrate that the proposed PUF scheme achieves good uniqueness (50.64 percent), uniformity (50.02 percent), and bit-aliasing ( <inline-formula><tex-math notation="LaTeX">$\approx$</tex-math></inline-formula> 49.80%). Particularly, the proposed method significantly improves the PUF reliability, achieving low bit error rate (BER <inline-formula><tex-math notation="LaTeX">$\leq$</tex-math></inline-formula> 2.13%) within the range of -20 <inline-formula><tex-math notation="LaTeX">$^\circ$</tex-math></inline-formula> C to 90 <inline-formula><tex-math notation="LaTeX">$^\circ$</tex-math></inline-formula> C.

A reconfigurable PUF structure with dual working modes based on entropy separation model

Privacy Protection Mutual Authentication (PPMA) in the Internet of Things uses physical unclonable functions (PUFs) and true random number generators (TRNGs) as security primitives, providing a lightweight solution for key generation and protection. At present, the designs for achieving PUF and TRNG simultaneously on field programmable gate array (FPGA) lack theoretical support, and have poor randomness and stability. Therefore, this paper provides a separation model of PUF entropy (manufacturing delay) and TRNG entropy (jitter delay) based on ring oscillators (ROs). Based on this model, a reconfigurable PUF structure is proposed, which can be reconstructed to a TRNG by changing the working mode. The proposed structure not only improves the area utilization, but also realizes the low-power consumption. Experiments on Xilinx Spartan-6 FPGAs and Xilinx Virtex-6 FPGAs show that the proposed structure has wonderful performance. The PUF has excellent uniqueness (average resolution is 50.21%) and reliability (the average repeatability rate is 96.98%). TRNG's output sequences have high randomness and pass all National Institute of Standards and Technology (NIST) tests (average pass rate is 99%).

Reconfigurable Optical Physical Unclonable Functions Enabled by VO2 Nanocrystal Films

Optical physical unclonable function (PUF) is one of the most promising hardware security solutions, which has been proven to be resistant to machine learning attacks. However, the disordered structures of the traditional optical PUFs are usually deterministic once they are manufactured and therefore exhibit fixed challenge-response behaviors. Herein, a reconfigurable PUF (R-PUF) is proposed and demonstrated by using the reversible phase transition behavior of VO2 nanocrystals combined with TiO2 disordered nanoparticles. Both the simulation and experiment results show that the near-infrared laser speckle pattern of the R-PUF can be almost completely altered after the phase transition of VO2 nanocrystals, resulting in a reconfigurable and reproducible optical response. The similarity of the response speckles shows an obvious hysteresis loop during the rise and drop of temperature, providing a simple way to regulate and control the response behaviors of the R-PUF. More importantly, the hysteretic characteristic provides a new dimension to describe the challenge-response behavior of the R-PUF besides the laser speckle, providing an effective way to improve the security and encoding capacity of the optical PUFs. The proposed R-PUF can be employed as a promising security primitive for high robustness and high-security authentication and encryption.

A Novel RFID Authentication Protocol Based on Reconfigurable RRAM PUF.

Radio frequency identification technology (RFID) has empowered a wide variety of automation industries. Aiming at the current light-weight RFID encryption scheme with limited information protection methods, combined with the physical unclonable function (PUF) composed of resistive random access memory (RRAM), a new type of high-efficiency reconfigurable strong PUF circuit structure is proposed in this paper. Experimental results show that the proposed PUF shows an almost ideal value (50%) of inter-chip hamming distance (HD) (µ/ = 0.5001/0.0340) among 1000 PUF keys, and intra-chip HD results are very close to the ideal value (0). The bit error rate (BER) is as low as across one million challenges. Based on the RRAM PUF, we propose and implement a light weight RFID authentication protocol. By virtue of RRAM’s model ability, the protocol replaces the One-way Hash Function with a response chain mutual encryption algorithm. The results of test and analysis show that the protocol can effectively resist multiple threats such as physical attacks, replay attacks, tracking attacks and asynchronous attacks, and has good stability. At the same time, based on RRAM’s unique resistance variability, PUF also has the advantage of being reconfigurable, providing good security for RFID tags.

A Reconfigurable Arbiter MPUF With High Resistance Against Machine Learning Attack

Physical unclonable function (PUF) is an emerging hardware security primitive which is increasingly used to authenticate and identify Internet of Things (IoT) devices. Spin-transfer torque magnetoresistive random access memory (STT-MRAM) provides new opportunities for novel PUFs due to inherent randomness sources, such as process variations, stochastic switching, and chaotic magnetization. In this article, we propose a hybrid STT-MRAM/complementary metal-oxide semiconductor (CMOS)-based reconfigurable arbiter PUF (MPUF) with enhanced performance metrics in terms of reliability, uniqueness, and uniformity. This design has a mean intra-hamming distance (HD) of 0.147%, a mean inter-HD of 50.21%, and passes the National Institute of Standards and Technology (NIST) statistical tests. The proposed arbiter MPUF features distinct advantages, such as reconfigurable architecture, challenge-dependent stage delays, and huge challenge-response pair (CRP) space. Moreover, the robustness of the proposed MPUF against machine learning (ML)-based modeling attacks is tested using three ML algorithms, namely support vector machine (SVM), linear regression (LR), and multilayer perceptron (MLP). Results show that the proposed reconfigurable arbiter MPUF is resistant to ML attacks and minimizes the ML attack prediction accuracy to less than 65.12% without XOR and less than 44.34% with XOR. Meanwhile, the correlation power analysis demonstrates that the proposed MPUF is also resilient to side-channel attacks.

Halide perovskite memristors as flexible and reconfigurable physical unclonable functions

Physical Unclonable Functions (PUFs) address the inherent limitations of conventional hardware security solutions in edge-computing devices. Despite impressive demonstrations with silicon circuits and crossbars of oxide memristors, realizing efficient roots of trust for resource-constrained hardware remains a significant challenge. Hybrid organic electronic materials with a rich reservoir of exotic switching physics offer an attractive, inexpensive alternative to design efficient cryptographic hardware, but have not been investigated till date. Here, we report a breakthrough security primitive exploiting the switching physics of one dimensional halide perovskite memristors as excellent sources of entropy for secure key generation and device authentication. Measurements of a prototypical 1 kb propyl pyridinium lead iodide (PrPyr[PbI3]) weak memristor PUF with a differential write-back strategy reveals near ideal uniformity, uniqueness and reliability without additional area and power overheads. Cycle-to-cycle write variability enables reconfigurability, while in-memory computing empowers a strong recurrent PUF construction to thwart machine learning attacks.

A Non Linear PUF Circuit Design for Two Factor Authentication in IoT Cryptography

Internet-of-Things (IoT) is growing network paradigm which enables mutual communication between the user and smart devices using the internet. The IoT devices are susceptible to the security threats, due to placement of restricted computational capabilities of the computing devices in IoT. The conventional encryption algorithm utilizes the high amount of resource block in it which increases the area and power. Moreover, Two Factor Authentication (TFA) scheme based authentication protocols does not have the efficiency to secure the data. Because the random number generated by the TFA is ideal for all IoT devices which are easy to hack by the unauthorized persons. In this Research paper, the Linear Feedback Shift Register (LFSR) based Reconfigurable Physical Unclonable Function (RPUF) is proposed to overcome the security issues caused in the IoT communication. The RPUF is designed based on the LFSR to generate the random number for every clock cycle. Normally, reconfigurable process helps to generate the different output values for every clock cycle. But, it failed to generate different outputs for same input values. Here, LFSR based RPUF helps to generated the different response values even the same challenge is given to the input side. The Lightweight TFA scheme is presented for IoT, where PUF has been considered as one of the major authentication factors. At last, Spartan 6 and Virtex 6 Field Programmable Gate Array (FPGA) performances are calculated for proposed TFA-RPUF-IoT and existing TFA-PUF-IoT protocols. In Spartan 6, TFA-RPUF-IoT protocol occupied 11 slices, 31 LUTs, 42 flip flops which are less compared to conventional TFA-PUF-IoT.

Evolution-Strategies-Driven Optimization on Secure and Reconfigurable Interconnection PUF Networks

Physical Unclonable Functions (PUFs) are known for their unclonability and light-weight design. However, several known issues with state-of-the-art PUF designs exist including vulnerability against machine learning attacks, low output randomness, and low reliability. To address these problems, we present a reconfigurable interconnected PUF network (IPN) design that significantly strengthens the security and unclonability of strong PUFs. While the IPN structure itself significantly increases the system complexity and nonlinearity, the reconfiguration mechanism remaps the input–output mapping before an attacker could collect sufficient challenge-response pairs (CRPs). We also propose using an evolution strategies (ES) algorithm to efficiently search for a network configuration that is capable of producing random and stable responses. The experimental results show that applying state-of-the-art machine learning attacks result in less than 53.19% accuracy for single-bit output prediction on a reconfigurable IPN with random configurations. We also show that, when applying configurations explored by our proposed ES method instead of random configurations, the output randomness is significantly improved by 220.8% and output stability by at least 22.62% in different variations of IPN.

Reconfigurable Physical Unclonable Function Based on Spin-Orbit Torque Induced Chiral Domain Wall Motion

A reliable design of physical unclonable function (PUF) based on spin-orbit torque (SOT) induced domain wall (DW) motion has been proposed and experimentally demonstrated. Magnetic DWs are nucleated and propagate in Ta/CoFeB/MgO heterostructures in which their device-to-device variation enables the PUF, while cycle-to-cycle variation in DW motion enables the reconfigurable design. Furthermore, field-free SOT switching has been observed in the chiral domain wall likely caused by the large Dzyaloshinskii-Moriya interaction (DMI) effect. The proposed DW motion based anti-counterfeiting device shows good promises as a CMOS-compatible PUF for hardware security.

XOR-Based Low-Cost Reconfigurable PUFs for IoT Security

With the rapid development of the Internet of Things (IoT), security has attracted considerable interest. Conventional security solutions that have been proposed for the Internet based on classical cryptography cannot be applied to IoT nodes as they are typically resource-constrained. A physical unclonable function (PUF) is a hardware-based security primitive and can be used to generate a key online or uniquely identify an integrated circuit (IC) by extracting its internal random differences using so-called challenge-response pairs (CRPs). It is regarded as a promising low-cost solution for IoT security. A logic reconfigurable PUF (RPUF) is highly efficient in terms of hardware cost. This article first presents a new classification for RPUFs, namely circuit-based RPUF (C-RPUF) and algorithm-based RPUF (A-RPUF); two Exclusive OR (XOR)-based RPUF circuits (an XOR-based reconfigurable bistable ring PUF (XRBR PUF) and an XOR-based reconfigurable ring oscillator PUF (XRRO PUF)) are proposed. Both the XRBR and XRRO PUFs are implemented on Xilinx Spartan-6 field-programmable gate arrays (FPGAs). The implementation results are compared with previous PUF designs and show good uniqueness and reliability. Compared to conventional PUF designs, the most significant advantage of the proposed designs is that they are highly efficient in terms of hardware cost. Moreover, the XRRO PUF is the most efficient design when compared with previous RPUFs. Also, both the proposed XRRO and XRBR PUFs require only 12.5% of the hardware resources of previous bitstable ring PUFs and reconfigurable RO PUFs, respectively, to generate a 1-bit response. This confirms that the proposed XRBR and XRRO PUFs are very efficient designs with good uniqueness and reliability.

Enhanced Reconfigurable Physical Unclonable Function Based on Stochastic Nature of Multilevel Cell RRAM

The physical unclonable function (PUF) based on resistive random-access memory (RRAM) possesses a distinctive advantage that can offer higher security and lower cost than the traditional complementary metal–oxide–semiconductor-based cryptographic devices and other conventional PUFs. The intrinsic stochasticity of RRAM devices successfully provides attractive properties to implement PUF. In this paper, we present a novel multistate-based RRAM PUF to realize strong tolerance against attack. By applying multilevel states with bit shuffling to the RRAM PUF, the randomness and uniqueness were enhanced close to ideal values. In addition, the bit error rate was dramatically reduced using the temperature compensation mechanism. Moreover, our new method not only enables the generation of larger challenge–response pairs (CRPs) with less footprint but also can reconfigure CRPs.

Duty-Cycle-Based Controlled Physical Unclonable Function

Physical unclonable functions (PUFs) provide a unique signature based on the variations during the fabrication process of the integrated circuits. The additional features of controllability and reconfigurability to a PUF implementation enable the reuse of the existing hardware as a new modified PUF, enhancing the capabilities of a PUF for more versatile security applications. In this paper, a variable duty-cycle-based ring oscillator circuit is proposed as a controlled and reconfigurable PUF primitive. One of the distinguishing features of the proposed PUF is that duty cycle comparisons are used, instead of the conventional frequency comparisons to generate the output bit response. The advantages of the utilizing duty cycle over the conventional frequency-based comparisons are investigated. The feasibility of the proposed PUF is evaluated using existing figures of merit providing a uniqueness of 49.3%, temperature reliability greater than 92% between 0 and 100 °C, and supply voltage reliability greater than 96% between 0.9 and 1 V.

Highly Reliable Multiport PUF Circuit Based on MOSFET Zero Temperature Coefficient Point

By using processing variations in the unitcircuits of the same structures and design parameters during manufacturing, Physical unclonable function (PUF) generates security keys with characteristic of uniqueness, randomness and unclonability. In this paper, a highly reliable multiport PUF scheme was proposed based on MOSFET Zero temperature coefficient (ZTC) point. It consists of input register, deviation-current generating module, arbiter array and obfuscation circuit. After reconfiguring deviation-current generating module by applying different input challenges, the PUF circuit updates keys without physical replacement. And multi-bit keys can be generated in one clock cycle. In TSMC-LP 65nm CMOS technology, the layout of 64-port reconfigurable PUF occupies 131μm×242μm with custom designing. Experimental results show that the PUF circuit has good statistical characteristic of uniqueness and randomness. It exhibits high reliability of 98.2% with respect to temperature variation from -40°C to 125°C and supply voltage variation from 1.08V to 1.32V, indicating that it can be reliably and effectively used in information security field.

Area-Efficient PUF-Based Key Generation on System-on-Chips with FPGAs

Physically unclonable functions (PUFs) are an innovative way to generate device unique keys using uncontrollable production tolerances. In this work, we present a method to use PUFs on modern FPGA-based system-on-chips (SoCs). The processor system part of the SoC is used to configure the FPGA part. We propose a reconfigurable PUF design that can be changed by using the partial reconfiguration (PR) feature of modern FPGAs. Multiple ring oscillator PUF (RO PUF) designs are loaded on the same logic blocks of the FPGA in order to make use of different resources, i.e., sources of entropy, on the FPGA. Their frequencies are read out individually and the differences between neighbored oscillators are used to generate a bit response. The responses of each design can be concatenated to a larger response vector that can be used to generate a cryptographic key. We present an implementation that is able to decrease the needed resources by 87.5% on a Xilinx Zynq.

Reconfigurable physical unclonable function based on probabilistic switching of RRAM

The probabilistic switching of resistive random access memory (RRAM) can be utilised to implement physical unclonable functions (PUFs). By setting the operation condition at a switching probability of 50%, devices in a RRAM array are randomly settled into state `0' or `1' after programming. The RRAM switching probability provides a natural source of randomness that could be exploited in the PUF to generate security primitives. The feasibility and characteristics of the proposed PUF are analysed by simulation based on measured RRAM switching probability. With good scalability and stochastic mechanisms, RRAM may prove to be a promising candidate for security applications.

Reconfigurable Binding against FPGA Replay Attacks

The FPGA replay attack, where an attacker downgrades an FPGA-based system to the previous version with known vulnerabilities, has become a serious security and privacy concern for FPGA design. Current FPGA intellectual property (IP) protection mechanisms target the protection of FPGA configuration bitstreams by watermarking or encryption or binding. However, these mechanisms fail to prevent replay attacks. In this article, based on a recently reported PUF-FSM binding method that protects the usage of configuration bitstreams, we propose to reconfigure both the physical unclonable functions (PUFs) and the locking scheme of the finite state machine (FSM) in order to defeat the replay attack. We analyze the proposed scheme and demonstrate how replay attack would fail in attacking systems protected by the reconfigurable binding method. We implement two ways to build reconfigurable PUFs and propose two practical methods to reconfigure the locking scheme. Experimental results show that the two reconfigurable PUFs can generate significantly distinct responses with average reconfigurability of more than 40%. The reconfigurable locking schemes only incur a timing overhead less than 1%.

Utilizing the Variability of Resistive Random Access Memory to Implement Reconfigurable Physical Unclonable Functions

The stochastic switching mechanism and intrinsic variability of resistive random access memory (RRAM) present severe challenges for memory applications, which, however, may be utilized to implement the physical unclonable function (PUF) for hardware security. A PUF based on RRAM resistance variability is proposed in this letter. Unlike PUFs based on manufacturing variation, this proposal exploits an intrinsic variability in physical mechanisms with reconfigurability. Key characteristics of the PUF design are assessed by simulation using measured RRAM properties and device model. Truly random variation of RRAM resistance is critical for PUF uniqueness (or unclonability). The reliability (or robustness) of the proposed PUF is affected by temperature and voltage dependence of RRAM resistance as well as retention characteristics. Large separation between inter-chip and intra-chip Hamming distance as the measure of uniqueness and reliability confirms the feasibility of the PUF proposal.