Reconfigurable Mesh Research Articles

Discrete Firefly Algorithm for Optimizing Topology Generation and Core Mapping of Network-on-Chip

Network-on-chip (NoC) proves to be the best alternative to replace the traditional bus-based interconnection in Multi-Processor System on a Chip (MPSoCs). Irregular NoC topologies are highly recommended and utilised in various applications as they are application specific. Optimized mapping of the cores in a NoC plays a major role in its performance. Firefly algorithm is a bio-inspired meta-heuristic approach. Discretized firefly algorithm is used in our proposed work. In this work, two optimization algorithms are proposed: Topology Generation using Discrete Firefly Algorithm (TGDFA) and Core Mapping using Discrete Firefly Algorithm (CMDFA) for multimedia benchmark applications, Video Object Plane Decoder (VOPD), Multimedia Window Display (MWD) and MP3 Encoder. The irregular topology generated using TGDFA is mapped using CMDFA onto a reconfigurable mesh with switches in between the routers to make it a fault tolerant one. The proposed TGDFA provides better optimization of communication cost. The speed-up on the average run time of the tasks and the time taken to attain the best solution by the proposed TGDFA is significant. The dynamic energy consumption of core mapping obtained by the proposed CMDFA is lesser when compared to the existing work. Finally, the optimized core mapping is implemented in a cycle accurate NoC simulator: Noxim. It is substantiated experimentally that the proposed CMDFA outperforms the previous work.

Computational analysis of optically controlled reconfigurable terahertz mesh filters using mesa arrays

AbstractWe report a novel approach for realizing tunable/reconfigurable terahertz (THz) mesh filters on the basis of micromachined mesa‐array structures. In this approach, different filter patterns are generated virtually using photogenerated free carriers in a semiconducting mesa‐array structure to achieve superior tunability and reconfigurability. Micromachined mesa‐array structures enable the formation of high fidelity, optically generated mesh filter structures for THz frequencies. To evaluate the proposed filter designs, the optically patterned spatial modulation properties of mesa‐array structures were first evaluated. Reconfigurable mesh filter prototypes were then designed and simulated using silicon mesa arrays with 50 × 50 μm2 square mesa unit cells. Simulations show that reconfigurable bandpass filters (BPFs) operating in the frequency range of 108–489 GHz with insertion losses of 0.82–1.13 dB can be achieved. By employing smaller unit cells, the frequency tuning range and filtering performance can be further improved. In addition to BPFs, other filter functionalities can also be realized utilizing the proposed approach. The wide tuning range and reconfigurability of the mesh filters demonstrate that the proposed approach is promising for developing tunable/reconfigurable circuits and components for advanced THz sensing, imaging, and communications.

New Decentralized Control of Mesh AC Microgrids: Study, Stability, and Robustness Analysis

In this paper, we investigated the power sharing issues in mesh islanded microgrids that contain several distributed generators (DGs) and loads connected to different points of common coupling (PCC). Firstly, an improved decentralized droop control algorithm is proposed to achieve the active and reactive power sharing of different DGs in reconfigurable mesh islanded microgrids. Accurate power sharing was obtained even though line parameters or the mesh microgrid configuration were unknown. Secondly a state-space model of the whole mesh microgrid was developed, considering several generators with their decentralized controllers, line feeders, and dynamic loads. This model was used to design parameters of droop controllers, to study the asymptotic stability and the robustness properties of the system. All strategies and analyses were validated by simulation based on the generic microgrid detailed in the standard IEEE 9bus test feeder.

FPGA Realization of the Reconfigurable Mesh Counting Algorithm

Pass transistor logic (PTL) is a circuit design technique wherein transistors are used as switches. The reconfigurable mesh (RM) is a model that exploits the power of PTLs signal switching, by enabling flexible bus connections in a grid of processing elements containing switches. RM algorithms have theoretical results proving that [Formula: see text] can speed up computations significantly. However, the RM assumes that the latency of broadcasting a signal through [Formula: see text] switches (bus length) is 1. This is an unrealistic assumption preventing physical realizations of the RM. We propose the restricted-RM (RRM) wherein the bus lengths are restricted to [Formula: see text], [Formula: see text]. We show that counting the number of 1-bits in an input of [Formula: see text] bits can be done in [Formula: see text] steps for [Formula: see text] by an [Formula: see text] RRM. An almost matching lower bound is presented, using a technique which adds to the few existing lower-bound techniques in this area. Finally, the algorithm was directly coded over an FPGA, outperforming an optimal tree of adders. This work presents an alternative way of counting, which is fundamental for summing, beating regular Boolean circuits for large numbers, where summing a vast amount of numbers is the basis of any accelerator in embedded systems such as neural-nets and streaming. a

Low Complexity 54–63-GHz Transmit/Receive 64- and 128-element 2-D-Scanning Phased-Arrays on Multilayer Organic Substrates With 64-QAM 30-Gbps Data Rates

This article presents 64- and 128-element transmit/receive phased-arrays built using SiGe 2 $\times $ 2 quad-chips flipped on a multilayer organic printed-circuit board (PCB). The arrays cover 54–63 GHz with 40–45-dBm effective isotropic radiated power (EIRP) in the TX mode. The antenna elements are stacked microstrip antennas spaced at $0.5\lambda $ in the horizontal plane and $0.7\lambda $ in the vertical plane at 60 GHz, resulting in a scan range of ±50° in azimuth and ±15° in elevation. A 64-QAM 30-Gbps communication link is achieved in the transmit mode when using its full instantaneous bandwidth. This article shows that it is possible to build phased-arrays at 60 GHz and beyond using simple 2 $\times $ 2 quad-chips with low antenna distribution loss, and not using complex chips with 16–32 antenna connections and high distribution loss. Applications include high data-rate point-to-multipoint links, reconfigurable mesh networks, and automotive radars.

Mapping application‐specific topology to mesh topology with reconfigurable switches

When designing a Network-on-Chip (NoC) architecture, designers must consider various criteria such as bandwidth, performance, energy consumption, cost, re-usability, and fault tolerance. In most of the design efforts, it is very difficult to meet all these interacting constraints and objectives at the same time. Some of these parameters can be optimised and met easily by regular NoC topologies due to their re-usability and fault-tolerance capabilities. On the other hand, other parameters such as energy consumption, performance, and chip area can be better optimised in irregular NoC topologies. In this work, the authors present a novel two-step method that combines the advantages of regular and irregular NoC topologies. In the first step, the authors’ method generates an energy and area optimised irregular topology for the given application by using a genetic algorithm. The generated topology uses the least amount of routers and links to minimise the area and energy; thus, it offers only one routing path between communicating nodes. Therefore, it does not fault tolerant. In the second step, their method maps the generated irregular topology to a reconfigurable mesh topology to make it fault tolerant. The detailed simulation results show the superiority of the proposed method over the existing work on several multimedia benchmarks.

Reconfigurable Photonic Circuit for Controlled Power Delivery to Laser-Driven Accelerators on a Chip

Dielectric laser acceleration (DLA) represents a promising approach to building miniature particle accelerators on a chip. However, similar to conventional RF accelerators, an automatic and reconfigurable control mechanism is needed to scale DLA technology towards high energy gains and practical applications. We present a system providing control of the laser coupling to DLA using integrated optics and introduce a novel component for power distribution using a reconfigurable mesh of Mach-Zehnder interferometers. We show how such a mesh may be sequentially and efficiently tuned to optimize power distribution in the circuit and find that this strategy has favorable scaling properties with respect to size of the mesh.

θ(1) time algorithm for 2D convex hull on a reconfigurable mesh computer architecture

θ(1) time algorithm for 2D convex hull on a reconfigurable mesh computer architecture

63.5–65.5-GHz Transmit/Receive Phased-Array Communication Link With 0.5–2 Gb/s at 100–800 m and ± 50° Scan Angles

This paper presents a 32-element phased array centered at 64 GHz using multiple SiGe chips on a single printed-circuit board. The antenna element is a series-fed patch array, which provides directivity in the elevation plane. The transmit array results in an effective isotropic radiated power of 42± 2 dBm at 63–65.5 GHz, while the receive array provides an electronic gain of 24 dB and a system noise figure <7.7 dB, including antenna loss, T/R switch, beamformer, and transceiver. The arrays can be scanned to ±50° in the azimuth using a 5-bit phase shifter on the SiGe chip without degradation in sidelobes and maintaining a near-ideal pattern. A communication link between two phased arrays at 100, 300, and 800 m is also demonstrated, and employs one array on the transmit side and another array on the receive side, together with external mixers and IF amplifiers. The link performance was measured for different scan angles and modulation formats. Data rates of 0.5–2 Gb/s using 16-QAM and QPSK waveforms are demonstrated at 100–800 m, with 2-Gb/s data rate at 300 m and ~500-Mb/s data rate at 800 m. To the best of our knowledge, this is the first system-level demonstration of a silicon-based Gb/s 60-GHz phased array over hundreds of meters. Application areas are in point-to-multipoint links, back-haul and front-haul links, and reconfigurable mesh networks for advanced communication systems.

\theta(1) time parallel algorithm for determining the diameters of multi-level image on the reconfigurable mesh computer machine

\theta(1) time parallel algorithm for determining the diameters of multi-level image on the reconfigurable mesh computer machine

Adaptive Booth Algorithm for Three-integers Multiplication for Reconfigurable Mesh

This paper presents a three-integers multiplication algorithm R = A * X * Y for Reconfigurable Mesh (RM). It is based on a three-integer multiplication algorithm for faster FPGA implementations. We show that multiplying three integers of n bits can be performed on a 3D RM of size (3n + log⁡ n + 1) × (2n+1 +3) × n+1 using 44 + 18 · log log MNO steps, where MNO is a bound which is related to the number of sequences of ‘1’s in the multiplied numbers. The value of MNO is bounded by n but experimentally we show that on the average it is n. Two algorithms for solving multiplication on a RM exists and their techniques are asymptotically better time wise, O(1) and O(log⁡* n), but they suffer from large hidden constants and slow data insertion time (O(n)) respectively. The proposed algorithm is relatively simple and faster on the average (via sampling input values) then the previous two algorithms thus contributes in making the RM a practical and feasible model. Our experiments show a significant improvement in the expected number of elementary operations for the proposed algorithm.

두 가시성 다각형의 교집합과 합집합을 구하는 효율적인 RMESH 알고리즘

We can consider the following problems for two given points p and q in a simple polygon P. (1) Compute the set of points of P which are visible from both p and q. (2) Compute the set of points of P which are visible from either p or q. They are corresponding to the problems which are to compute the intersection and the union of two visibility polygons. In this paper, we consider algorithms for solving these problems on a reconfigurable mesh(in short, RMESH). The algorithm in [1] can compute the intersection of two general polygons in constant time on an RMESH with size O(), where n is the total number of vertices of two polygons. In this paper, we construct the planar subdivision graph in constant time on an RMESH with size O() using the properties of the visibility polygon for preprocessing. Then we present O() time algorithms for computing the union as well as the intersection of two visibility polygons, which improve the processor-time product from O() to O().

Constant Time Algorithm for Computing a Collision-Free Path on R-Mesh with Path Quality Analysis

The reconfigurable mesh (R-Mesh) was shown to be a very powerful model capable of extremely fast solutions to many problems. R-Mesh has a wide range of applications such as arithmetic problems, image processing and robotics. The 2D R-Mesh was shown to be able to solve the path planning problem very fast. In this paper, we propose an algorithm to compute a collision-free path, P, between a source and a destination in an environment with the existence of obstacles. Independent of the number of obstacles, k, the proposed algorithm runs in constant time and requires O( log 2N) pre-processing time where N is the size of the R-Mesh. This is in contrast to the previous work that requires O(k) time with the same pre-processing time. We then consider the quality of the generated path. We present a constant-time modification to enhance the length of the path and analyze the generated path P in terms of the number of bends in P. We derive the number of bends in P for any set of obstacles. We also derive a necessary condition for the minimum number of bends in the path P, i.e., a lower bound on the number of bends. We finally identify a class of obstacles for which the above necessary condition is sufficient as well (tight bound).

A fine grained parallel fuzzy segmentation algorithm on reconfigurable mesh computer

A fine grained parallel fuzzy segmentation algorithm on reconfigurable mesh computer

An FPGA-Based Reconfigurable Mesh Many-Core

The reconfigurable mesh is a parallel model of computation, which exploits a massive amount of rather simple processing elements connected through a reconfigurable interconnection network. During the last decades, the model received strong interest and many researchers have devised algorithms for it. However, most of this work focuses on theoretical aspects. Due to some idealistic modeling assumptions only a few attempts have been made to implement the model and to study the practical use of reconfigurable meshes. In this paper, we leverage the reconfigurable mesh model to study potential architectures and programming models for future many-cores. We design a reconfigurable mesh in form of a scalable soft core array with a reconfigurable interconnect and implement it on FPGA technology in order to create a prototype platform. We present an overall hardware/software tool flow for generating and programming reconfigurable mesh prototypes. The new language ARMLang and a corresponding compiler facilitate the programming of the massively parallel processor arrays. To our knowledge, this work is the first practical study of word-level reconfigurable meshes. To analyze the performance of our implementation we study four algorithmic kernels from the application domains arithmetic, sorting, graph algorithms and imaging. For each kernel, we devise a reconfigurable mesh program in ARMLang, compile it to our soft core array and measure its runtime depending on the mesh size. Then, we compare the runtimes to two sequential implementations of the algorithms, which are executed on two single core systems. The results show that many-cores leveraging the reconfigurable mesh model can efficiently use a vast number of processing elements and that, for the chosen algorithms, they come close to optimally parallelized programs.

Joint Scheduling and Routing for QoS Guaranteed Packet Transmission in Energy Efficient Reconfigurable WDM Mesh Networks

The explosion of Internet traffic calls for quality of service (QoS)-guaranteed packet transmission in wavelength division multiplexing (WDM) networks with high energy and bandwidth efficiency. Conventional routing and wavelength assignment (RWA) algorithms focus on circuit switching, which does not well meet this requirement due to the bursty nature of IP traffic. Based on a novel traffic matrix decomposition technique, we study the joint design of traffic scheduling and routing in a reconfigurable WDM optical network to improve energy and bandwidth efficiency. Specifically, every node in the network is equipped with a set of parallel tunable lasers, each with a reconfiguration overhead. A dynamic matrix is adopted to model the traffic among the nodes and is decomposed into a set of transmission configurations (i.e., traffic scheduling). The configurations are then fulfilled by tuning the parallel lasers and routing the scheduled traffic under the topology constraint, to achieve loss-free packet transmissions with bounded delay (i.e., QoS guarantee). We reveal that a tradeoff exists between the packet delay and the required number of tunable lasers. The latter is then minimized under a given packet delay to save energy. As far as we know, this is the first work to adopt traffic matrix decomposition in WDM networks to save energy. The proposed framework is validated by extensive simulation studies.

The Well-Connected Processor Array

A new theoretical model for reconfigurable processor arrays is introduced. Most of the models considered in the literature are similar to the reconfigurable mesh (RMESH), in which each processing element (PE) is connected to its four neighbors by reconfigurable buses. In the new model, called the “well-connected processor array” (wecpar), every PE is connected to each neighbor by ${\mbi{k}} {\bf \geq 1}$ point-to-point lines, and it also controls the switching between those lines. ${\mbi{k}}$ is called the connectivity of the wecpar. Any line entering the PE can either be connected to the PE itself, or it can be connected by the PE to another line, thus enabling complex switching configurations. This model is suitable for arrays in which the computation and memory areas of a PE are very much larger than a switch area. The concept of a burden placed on a PE by the lines connected to or passing through it is introduced. This is used to derive a lower bound of ${\mbi{k}}=\Omegab({\mbi{d}}^{\bf 3/2}/{\mbi{e}})$ on the connectivity required by a wecpar to embed any graph of degree ${\bf \geq}{\mbi{d}}$ with expansion ${\mbi{e}}$ ; for ${\mbi{e}} {\bf = 1}$ , this result is sharp. Various other issues are examined: graph embeddings, algorithms, broadcasting, routing, and self-simulation. A novel transportation-type routing method utilizes the connectivity for efficient routing. A sample algorithmic result is that an ${\mbi{n}}$ -point FFT can be done in logarithmic time on a wecpar of ${\mbi{n}}$ PEs with a connectivity of $\sqrt{{\mbi{n}}/{\bf 2}}$ .

Parallel progressive multiple sequence alignment on reconfigurable meshes

BackgroundOne of the most fundamental and challenging tasks in bio-informatics is to identify related sequences and their hidden biological significance. The most popular and proven best practice method to accomplish this task is aligning multiple sequences together. However, multiple sequence alignment is a computing extensive task. In addition, the advancement in DNA/RNA and Protein sequencing techniques has created a vast amount of sequences to be analyzed that exceeding the capability of traditional computing models. Therefore, an effective parallel multiple sequence alignment model capable of resolving these issues is in a great demand.ResultsWe design O(1) run-time solutions for both local and global dynamic programming pair-wise alignment algorithms on reconfigurable mesh computing model. To align m sequences with max length n, we combining the parallel pair-wise dynamic programming solutions with newly designed parallel components. We successfully reduce the progressive multiple sequence alignment algorithm's run-time complexity from O(m × n4) to O(m) using O(m × n3) processing units for scoring schemes that use three distinct values for match/mismatch/gap-extension. The general solution to multiple sequence alignment algorithm takes O(m × n4) processing units and completes in O(m) time.ConclusionsTo our knowledge, this is the first time the progressive multiple sequence alignment algorithm is completely parallelized with O(m) run-time. We also provide a new parallel algorithm for the Longest Common Subsequence (LCS) with O(1) run-time using O(n3) processing units. This is a big improvement over the current best constant-time algorithm that uses O(n4) processing units.

Parallel c-means algorithm for image segmentation on a reconfigurable mesh computer

In this paper, we propose a parallel algorithm for data classification, and its application for Magnetic Resonance Images (MRI) segmentation. The studied classification method is the well-known c-means method. The use of the parallel architecture in the classification domain is introduced in order to improve the complexities of the corresponding algorithms, so that they will be considered as a pre-processing procedure. The proposed algorithm is assigned to be implemented on a parallel machine, which is the reconfigurable mesh computer (RMC). The image of size ( m × n) to be processed must be stored on the RMC of the same size, one pixel per processing element (PE).

Parallel c-means algorithm for image segmentation on a reconfigurable mesh computer

Parallel c-means algorithm for image segmentation on a reconfigurable mesh computer