Reconfigurable Logic Resources Research Articles

VITI: A Tiny Self-Calibrating Sensor for Power-Variation Measurement in FPGAs

On-chip sensors, built using reconfigurable logic resources in field programmable gate arrays (FPGAs), have been shown to sense variations in signalpropagation delay, supply voltage and power consumption. These sensors have been successfully used to deploy security attacks called Remote Power Analysis (RPA) Attacks on FPGAs. The sensors proposed thus far consume significant logic resources and some of them could be used to deploy power viruses. In this paper, a sensor (named VITI) occupying a far smaller footprint than existing sensors is presented. VITI is a self-calibrating on-chip sensor design, constructed using adjustable delay elements, flip-flops and LUT elements instead of combinational loops, bulky carry chains or latches. Self-calibration enables VITI the autonomous adaptation to differing situations (such as increased power consumption, temperature changes or placement of the sensor in faraway locations from the circuit under attack). The efficacy of VITI for power consumption measurement was evaluated using Remote Power Analysis (RPA) attacks and results demonstrate recovery of a full 128-bit Advanced Encryption Standard (AES) key with only 20,000 power traces. Experiments demonstrate that VITI consumes 1/4th and 1/16th of the area compared to state-of-the-art sensors such as time to digital converters and ring oscillators for similar effectiveness.

Parallel architecture of power‐of‐two multipliers for FPGAs

This research work presents a novel approach to design efficient power-of-two multipliers on modern field-programmable gate arrays (FPGA) devices. Several ways of exploiting fixed-point power-of-two multiplications have been recently demonstrated to reduce the computational complexity of several computationally intensive applications, such as computer vision, deep learning, and many others. Modern FPGA devices provide speed-optimised intellectual property (IP) cores based on embedded modules, such as digital signal processing blocks, and area-optimised IP cores based on reconfigurable logic resources, such as look-up tables and flip-flops. Unfortunately, due either to their limited available amount or to their limited running frequency, these IP cores do not allow the overall computational capability offered by an FPGA device to be completely exploited. While the speed-optimised version of the multiplier proposed here is fast enough to increase the number of operations performed per second by up to 4.3 times, with respect to the conventional designs, its area-optimised implementation reduces resources requirements and energy consumption by up to 22 and 40%.

A Distributed Reconfigurable Active Solid State Drive Platform for Data Intensive Applications

The ability to efficiently extract useful information from volumes of data distributed across myriad networks is hindered by the latencies inherent to magnetic storage devices and computer networks. We propose overcoming these limitations by leveraging solid-state drive (SSD) and field-programmable gate array (FPGA) technologies to process large streams of data directly at the storage sites. Our proposed reconfigurable, active, solid-state drive (RASSD) platform consists of distributed nodes that couple SSDs with FPGAs. While SSDs store data, FPGAs implement processing elements that couple soft-core RISC processors with dynamically reconfigurable logic resources. The processors execute data-processing software drivelets, and the logic resources implement hardware for accelerating performance-critical operations. Executing appropriate drivelets and using matching hardware accelerators enables us to efficiently process streams of data stored across SSDs. To manage the configuration of RASSD nodes and provide a transparent interface to applications, our platform also consists of distributed middleware software. Client local middleware (CLM) resides on client host machines to interpret application data processing requests, locate storage sites, and exchange data-processing requests and results with middleware servers (MWS). MWS connect to clusters of RASSD nodes and contain libraries of drivelets and accelerator configuration bit streams. An MWS loads appropriate drivelet and accelerator bit streams onto a RASSD node's FPGA, aggregates processed data, and returns it to a CLM. To evaluate our platform, we implemented a simple system consisting of a host computer connected to a RASSD node over a peer-to-peer network. We ran a keyword search application on the host computer, which also provided middleware functionality. We then evaluated this platform under three configurations. In configuration C1, the RASSD node was only used to store data while all data was processed by the MWS running on the host computer. In configuration C2, the data was processed by a drivelet running on the RASSD node. Finally, in configuration C3, the data was processed both by a drivelet and a hardware accelerator. Our experimental results show that C3 is 2x faster than C2, and 6x faster than C1. This demonstrates our platform's potential for enhancing the performance of data-intensive applications over current systems.

Software-Controlled Dynamically Swappable Hardware Design in Partially Reconfigurable Systems

We propose two basic wrapper designs and an enhanced wrapper design for arbitrary digital hardware circuit designs such that they can be enhanced with the capability for dynamic swapping controlled by software. A hardware design with either of the proposed wrappers can thus be swapped out of the partially reconfigurable logic at runtime in some intermediate state of computation and then swapped in when required to continue from that state. The context data is saved to a buffer in the wrapper at interruptible states, and then the wrapper takes care of saving the hardware context to communication memory through a peripheral bus, and later restoring the hardware context after the design is swapped in. The overheads of the hardware standardization and the wrapper in terms of additional reconfigurable logic resources and the time for context switching are small and generally acceptable. With the capability for dynamic swapping, high priority hardware tasks can interrupt low-priority tasks in real-time embedded systems so that the utilization of hardware space per unit time is increased.