Reconfigurable Hardware Platform Research Articles

Calibration-Free and Hardware-Efficient Neural Spike Detection for Brain Machine Interfaces.

Recent translational efforts in brain-machine interfaces (BMI) are demonstrating the potential to help people with neurological disorders. The current trend in BMI technology is to increase the number of recording channels to the thousands, resulting in the generation of vast amounts of raw data. This in turn places high bandwidth requirements for data transmission, which increases power consumption and thermal dissipation of implanted systems. On-implant compression and/or feature extraction are therefore becoming essential to limiting this increase in bandwidth, but add further power constraints - the power required for data reduction must remain less than the power saved through bandwidth reduction. Spike detection is a common feature extraction technique used for intracortical BMIs. In this article, we develop a novel firing-rate-based spike detection algorithm that requires no external training and is hardware efficient and therefore ideally suited for real-time applications. Key performance and implementation metrics such as detection accuracy, adaptability in chronic deployment, power consumption, area utilization, and channel scalability are benchmarked against existing methods using various datasets. The algorithm is first validated using a reconfigurable hardware (FPGA) platform and then ported to a digital ASIC implementation in both 65 nm and 0.18 μm CMOS technologies. The 128-channel ASIC design implemented in a 65 nm CMOS technology occupies 0.096 mm2 silicon area and consumes 4.86 μW from a 1.2 V power supply. The adaptive algorithm achieves a 96% spike detection accuracy on a commonly used synthetic dataset, without the need for any prior training.

Hardware-Accelerated Data Decoding and Reconstruction for Automotive LiDAR Sensors

The automotive industry is facing an unprecedented technological transformation towards fully autonomous vehicles. Optimists predict that, by 2030, cars will be sufficiently reliable, affordable, and common to displace most current human driving tasks. To cope with these trends, autonomous vehicles require reliable perception systems to hear and see all the surroundings, being light detection and ranging (LiDAR) sensors a key instrument for recreating a 3D visualization of the world. However, for a reliable operation, such systems require LiDAR sensors to provide high-resolution 3D representations of the car's vicinity, which results in millions of data points to be processed in real-time. With this article we propose the ALFA-Pi, a data packet decoder and reconstruction system fully deployed on an embedded reconfigurable hardware platform. By resorting to field-programmable gate array (FPGA) technology, ALFA-Pi is able to interface different LiDAR sensors at the same time, while providing custom representation outputs to high-level perception systems. By accelerating the LiDAR interface, the proposed system outperforms current software-only approaches, achieving lower latency in the data acquisition and data decoding tasks while reaching high performance ratios.

Reconfigurable 2D-ferroelectric platform for neuromorphic computing

To meet the requirement of data-intensive computing in the data-explosive era, brain-inspired neuromorphic computing have been widely investigated for the last decade. However, incompatible preparation processes severely hinder the cointegration of synaptic and neuronal devices in a single chip, which limited the energy-efficiency and scalability. Therefore, developing a reconfigurable device including synaptic and neuronal functions in a single chip with same homotypic materials and structures is highly desired. Based on the room-temperature out-of-plane and in-plane intercorrelated polarization effect of 2D α-In2Se3, we designed a reconfigurable hardware platform, which can switch from continuously modulated conductance for emulating synapse to spiking behavior for mimicking neuron. More crucially, we demonstrate the application of such proof-of-concept reconfigurable 2D ferroelectric devices on a spiking neural network with an accuracy of 95.8% and self-adaptive grow-when required network with an accuracy of 85% by dynamically shrinking its nodes by 72%, which exhibits more powerful learning ability and efficiency than the static neural network.

Compression of Deep Neural Networks based on quantized tensor decomposition to implement on reconfigurable hardware platforms

Deep Neural Networks (DNNs) have been vastly and successfully employed in various artificial intelligence and machine learning applications (e.g., image processing and natural language processing). As DNNs become deeper and enclose more filters per layer, they incur high computational costs and large memory consumption to preserve their large number of parameters. Moreover, present processing platforms (e.g., CPU, GPU, and FPGA) have not enough internal memory, and hence external memory storage is needed. Hence deploying DNNs on mobile applications is difficult, considering the limited storage space, computation power, energy supply, and real-time processing requirements. In this work, using a method based on tensor decomposition, network parameters were compressed, thereby reducing access to external memory. This compression method decomposes the network layers’ weight tensor into a limited number of principal vectors such that (i) almost all the initial parameters can be retrieved, (ii) the network structure did not change, and (iii) the network quality after reproducing the parameters was almost similar to the original network in terms of detection accuracy. To optimize the realization of this method on FPGA, the tensor decomposition algorithm was modified while its convergence was not affected, and the reproduction of network parameters on FPGA was straightforward. The proposed algorithm reduced the parameters of ResNet50, VGG16, and VGG19 networks trained with Cifar10 and Cifar100 by almost 10 times.

DIOR: A Hardware-Assisted Weather Denoising Solution for LiDAR Point Clouds

The interest in developing and deploying fully autonomous vehicles on our public roads has come to a full swing. Driverless capabilities, widely spread in modern vehicles through advanced driver-assistance systems (ADAS), require highly reliable perception features to navigate the environment, being light detection and ranging (LiDAR) sensors a key instrument in detecting the distance and speed of nearby obstacles and in providing high-resolution 3D representations of the surroundings in real-time. However, and despite being assumed as a game-changer in the autonomous driving paradigm, LiDAR sensors can be very sensitive to adverse weather conditions, which can severely affect the vehicle’s perception system behavior. Aiming at improving the LiDAR operation in challenging weather conditions, which contributes to achieving higher driving automation levels defined by the Society of Automotive Engineers (SAE), this article proposes a weather denoising method called Dynamic light-Intensity Outlier Removal (DIOR). DIOR combines two approaches of the state-of-the-art, the dynamic radius outlier removal (DROR) and the low-intensity outlier removal (LIOR) algorithms, supported by an embedded reconfigurable hardware platform. By resorting to field-programmable gate array (FPGA) technology, DIOR can outperform state-of-the-art outlier removal solutions, achieving better accuracy and performance while guaranteeing the real-time requirements.

Intelligent adjustable-speed drive on an FPGA

This paper addresses the design, simulation and implementation of a PI-like fuzzy controller to adjust the velocity of an armature-controlled DC motor using hardware/software co-design. Fuzzy control and digital pulse width modulation (PWM) techniques are used as computational solution, while the implementation is carried on a reconfigurable hardware platform. This controller is designed with four considerations in mind: design integration, robustness, reduced complexity and flexibility. Computationally intensive tasks are implemented as hardware accelerators using VHDL, data flow and control are implemented in software using system-on-programmable-chip (SoPC) approach. With this paradigm, we get the robustness of fuzzy control, the best of software programmability of Nios®-II and the hardware reconfigurability of the FPGA. The model was synthesised using Quartus®II and targeted at a Cyclone-II FPGA. Computer simulation results show the effectiveness and merit of this process. The real-time applicability of this controller is exemplified on a motor provided with a tachogenerator mounted on its shaft.

Virtualizing and Scheduling FPGA Resources in Cloud Computing Datacenters

Cloud service providers consistently leverage their computing infrastructures by adding reconfigurable hardware platforms such as field-programmable gate arrays (FPGAs) to their existing infrastructures. Adding FPGAs to a cloud environment involves non-trivial challenges. The first challenge is virtualizing FPGAs as part of the cloud resources. As a standard virtualization framework is lacking, there is a need for an efficient framework for virtualizing FPGAs. Furthermore, FPGA resources are used in conjunction with central processing units (CPUs) and graphics processing units (GPUs) to accelerate the execution of tasks. Therefore, to gain the benefits of these powerful accelerating platforms, the second challenge is to optimize the allocation of tasks into the capable resources within a cloud data center. This work proposes an FPGA virtualization framework that abstracts the physical FPGAs into virtual pools of FPGA resources. The work further presents an integer linear programming (ILP) optimization model to minimize the makespan of tasks where FPGA resources are part of the cloud data center. Given the complex nature of the problem, a simulated annealing (SA) metaheuristic is developed to achieve gains in performance compared to the exact method and to scale up and handle many tasks and resources while providing near-optimal solutions. Experimental results show that SA has reduced the makespan of a large dataset with 1000 tasks and 100 resources by up to 30% when compared to first-come-first-served (FCFS) and shortest-deadline-first (SDF) algorithms. Lastly, to quantify the performance of FPGA-enabled cloud datacenters, the work extends the CloudSim simulator (an open-source cloud simulator) to enable FPGA as a resource in its environment. The proposed virtualization framework and the SA scheduler are integrated into the environment. Simulation results show that the execution time of tasks is reduced by up to 78% when FPGA accelerators are used.

Embedded linear model predictive control in field-programmable gate array using register-transfer level implementation and floating-point representation applied to a quadrotor system model

Model predictive control is increasingly becoming a popular control strategy for a wide range of applications in both industry and academia, mainly motivated by its ability to systematically handle constraints imposed on a system, regardless of its nature. However, this generates high computational demands, limiting the applicability of model predictive control. Field-programmable gate arrays are reconfigurable hardware platforms that allow the parallel implementation of model predictive control, accelerating such algorithms, but most works found in the literature opt to use high-level synthesis tools and fixed-point numeric representation to generate embedded controllers, resulting in faster-designed solutions but not exactly efficient and flexible ones, that can be applied to different scenarios. Regarding such matter, this work proposes the manual implementation (register-transfer level implementation) of linear model predictive control and the usage of floating-point numeric representation applied to a quadrotor system. The initial results obtained using the proposed controller are presented in this article, achieving 29.34 ms of calculation time at 50 MHz for the attitude control of a quadrotor model containing twelve states and four control outputs.

Performance analysis of Vedic mathematics algorithms on re-configurable hardware platform

For the overall performance of systems like microprocessors and digital signal processors (DSPs) platforms, arithmetic units, all must be efficient in terms of speed, power, and area. Multipliers and dividers are inevitable hardware employed in such systems. This paper focuses on Vedic mathematics algorithms for multiplication and division for power-efficient, faster, and area-efficient design. For four- and eight-bit Vedic multiplication algorithms, Urdhva Tiryagbhyam and Nikhilam Sutras are employed in this paper. For eight-bit Vedic division algorithms, Nikhilam and Dhwajank Sutras are used. The Vedic mathematics algorithms are also compared to conventional methods of multiplication (like Array multiplier) and division (using Booth multiplication algorithm). As an application of DSP, the linear convolution operation is implemented using both conventional and Vedic algorithms. It has been observed that the Vedic algorithms operate faster, consume less power, and occupy less area on a targeted hardware platform. The implementations were carried out using the Verilog HDL language and Xilinx’s Vivado EDA tool. To measure various performance parameters, Cadence simvision (using 180-nm GPDK CMOS Technology) and Xilinx’s ISE tool were also used.

Multifuse multilayer multikernel RVFLN+ of process modes decomposition and approximate entropy data from iEEG/sEEG signals for epileptic seizure recognition

In this paper, the extracted features using variational mode decomposition (VMD) and approximate entropy (ApEn) privileged information of the input EEG signals are combined with multilayer multikernel random vector functional link network plus (MMRVFLN+) classifier to recognize the epileptic seizure epochs efficaciously. In our experiment Bonn University single-channel intracranial electroencephalogram (iEEG) and Children's Hospital Boston-Massachusetts Institute of Technology (CHB-MIT) multichannel scalp EEG (sEEG) recordings are considered to evaluate the efficacy of the proposed method. The VMD is applied on chaotic, non-stationary, nonlinear, and complex EEG signal to decompose it into three band-limited intrinsic mode functions (BLIMFs). The Hilbert transform (HT) is applied on BLIMFs to extract informative spectral and temporal features. The ApEn is computed from the raw EEG signals as the privileged information and given to the multi-hidden layer structure to obtain the most discriminative compressed form. The scatter plots show the distinct nature of compressed privileged ApEn information among the seizure pattern classes. The linear as well as nonlinear mapping, local and global kernel function, high-learning speed, less computationally complex MMRVFLN+ classifier is proposed to recognize the seizure events accurately by importing the efficacious features with ApEn as the input. The advanced signal processing algorithm i.e., Hilbert Huang transform (HHT) with ApEn and MMRVFLN+ are combined to compare the performance with the proposed VMDHTApEn-MMRVFLN+ method. The proposed method has remarkable recognition ability, superior classification accuracy, and excellent overall performance as compared to other methods. The digital architecture of the multifuse MMRVFLN+ is developed and implemented on a high-speed reconfigurable FPGA hardware platform to validate the effectiveness of the proposed method. The superior classification accuracy, the negligible false positive rate per hour (FPR/h), simplicity, feasibility, robustness, and practicability of the proposed method validate its ability to recognize the epileptic seizure epochs automatically.

The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design

Modern embedded and cyber-physical systems require every day more performance, power efficiency and flexibility, to execute several profiles and functionalities targeting the ever growing adaptivity needs and preserving execution efficiency. Such requirements pushed designers towards the adoption of heterogeneous and reconfigurable substrates, which development and management is not that straightforward. Despite acceleration and flexibility are desirable in many domains, the barrier of hardware deployment and operation is still there since specific advanced expertise and skills are needed. Related challenges are effectively tackled by leveraging on automation strategies that in some cases, as in the proposed work, exploit model-based approaches.This paper is focused on the Multi-Dataflow Composer (MDC) tool, that intends to solve issues related to design, optimization and operation of coarse-grain reconfigurable hardware accelerators and their easy adoption in modern heterogeneous substrates. MDC latest features and improvements are introduced in detail and have been assessed on the so far unexplored robotics application field. A multi-profile trajectory generator for a robotic arm is implemented over a Xilinx FPGA board to show in which cases coarse-grain reconfiguration can be applied and which can be the parameters and trade-offs MDC will allow users to play with.

Analysis of software and hardware-accelerated approaches to the simulation of unconventional interconnection networks

The design of new computer architectures relies heavily on simulation. New architectures that incorporate unconventional features or novel designs can not usually use established simulators and, therefore, designers have to adapt an existing one or develop their own from scratch. Traditionally, software-based simulators have been the main platform for architectural exploration. However, the introduction of high-level hardware description languages, such as Bluespec, together with improvements in reconfigurable hardware platforms, provides an opportunity to challenge the traditional notion and consider hardware-accelerated simulators for this purpose. This paper presents a comprehensive analysis of three simulators, a hardware-accelerated one, a high-fidelity software-based one and a mature, generic software one, each of them developed to evaluate different aspects of a novel, unconventional architecture: the SpiNNaker massively-parallel computer. The analysis includes a discussion of the different modelling and implementation trade-offs and a comparison with the real system.

Low power DNA protein sequence alignment using FSM state transition controller

In this paper we proposed an efficient computation technique for DNA patterns on reconfigurable hardware (FPGAs) platform. The paper also presents the results of a comparative study between existing dynamic and heuristic programming methods of the widely-used Smith-Waterman pair-wise sequence alignment algorithm with FSM-based core implementation. Traditional software implication-based sequence alignment methods can not meet the actual data rate requirements. Hardware-based approach will give high scalability and one can process parallel tasks with a large number of new databases. This paper explains finite state machine (FSM)-based core processing element to classify the protein sequence. In addition, we analyse the performance of bit-based sequence alignment algorithms and present the inner stage pipelined field programmable gate array (FPGA) architecture for sequence alignment implementations. Here, synchronised controllers are used to carry out parallel sequence alignment. The complete architecture is designed to carry out parallel processing in hardware, with FSM-based bit wised pattern comparison with scalability as well as with a minimum number of computations. Finally, the proposed design proved to be high performance and its efficiency in terms of resource utilisation is proved on FPGA implementation.

A reconfigurable hardware platform for low-power wide-area wireless sensor networks

Low power, large-area wireless sensor networks (WSNs) have been experiencing rapid growth in a wide range of applications, such as environmental monitoring applications and natural disaster early warning systems. The WSN consists of numerous nodes with sensing, computation, actuation, and radio communication capabilities. Dynamically reconfigurable hardware and context-aware operation to optimize performance and functionality and to prolong the lifetime of sensor nodes are critical goals in the design of distributed sensing systems, especially for battery-based systems being deployed in complex geographic areas where are hard to approach. In recent years, Programmable System-on-Chip (PSoC) technology is emerging as an efficient solution for achieving the dynamic hardware reconfiguration of a sensor node in a single chip. That aims at optimizing the use of resources, minimizing of energy waste, and system size according to the requirements of the applications. This paper presents the implementation of a configurable hardware platform for remote sensing systems based on PSoC and LoRa technology. The proposed hardware design stands out for high performance, ultralow-power, providing long-range communication as well as reconfigurable interfaces in communicating and manipulating with various types of sensors and actuators. The experiments to evaluate the functional requirements and energy consumption of the design were investigated with positive results.

FPGA Implementation of Weighted Online Sequential Extreme Learning Machine for Data Classification

To design an efficient embedded module field-programmable gate array (FPGA) plays significant role. FPGA, a high speed reconfigurable hardware platform has been used in various field of research to produce the throughput efficiently. A now-a-days artificial neural network (ANN) is the most prevalent classifier for many analytical applications. In this paper, weighted online sequential extreme learning machine (WOS-ELM) classifier is presented and implemented in hardware environment to classify the different real-world bench-mark datasets. The faster learning speed, remarkable classification accuracy, lesser hardware resources, and short-event detection time, aid the hardware implementation of WOS-ELM classifier to design an embedded module. Finally, the developed hardware architecture of the WOS-ELM classifier is implemented on a high speed reconfigurable Xilinx Virtex (ML506) FPGA board to demonstrate the feasibility, effectiveness, and robustness of WOS-ELM classifier to classify the data in real-time environment.

Accelerating an FPGA‐Based SAT Solver by Software and Hardware Co‐design

The Boolean Satisfiability (SAT) problem is the key problem in computer theory and application. Field-programmable gate array (FPGA) has been addressed frequently to accelerate the SAT solving process in the last few years owing to its parallelism and flexibility. We have proposed a novel SAT solver based on an improved local search algorithm on the reconfigurable hardware platform. The new software preprocessing procedure and hardware architecture are involved to solve large-scale SAT problems instances. As compared with the past solvers, the proposed solver has the following advantages: the preprocessing technology can strongly improve the efficiency of solver; the strategy of strengthening the variable selection can avoid the same variable flipped continuously and repeatedly. It reduces the possibility of search falling into local minima. The experimental results indicate that the solver can solve problems of up to 32K variables/128K clauses without off-chip memory banks, and has better performance than previous works.

A Parallel Architecture for the Partitioning Around Medoids (PAM) Algorithm for Scalable Multi-Core Processor Implementation with Applications in Healthcare.

Clustering is the most common method for organizing unlabeled data into its natural groups (called clusters), based on similarity (in some sense or another) among data objects. The Partitioning Around Medoids (PAM) algorithm belongs to the partitioning-based methods of clustering widely used for objects categorization, image analysis, bioinformatics and data compression, but due to its high time complexity, the PAM algorithm cannot be used with large datasets or in any embedded or real-time application. In this work, we propose a simple and scalable parallel architecture for the PAM algorithm to reduce its running time. This architecture can easily be implemented either on a multi-core processor system to deal with big data or on a reconfigurable hardware platform, such as FPGA and MPSoCs, which makes it suitable for real-time clustering applications. Our proposed model partitions data equally among multiple processing cores. Each core executes the same sequence of tasks simultaneously on its respective data subset and shares intermediate results with other cores to produce results. Experiments show that the computational complexity of the PAM algorithm is reduced exponentially as we increase the number of cores working in parallel. It is also observed that the speedup graph of our proposed model becomes more linear with the increase in number of data points and as the clusters become more uniform. The results also demonstrate that the proposed architecture produces the same results as the actual PAM algorithm, but with reduced computational complexity.

Scalable embedded computing through reconfigurable hardware: Comparing DF-Threads, cilk, openmpi and jump

Data-Flow Threads (DF-Threads) is a new execution model that permits to seamlessly distribute the workload across several cores (in a multi-core) and several nodes (in a multi-node/multi-board configuration).In this paper, the advance in deploying this execution model is shown while developing it by using a combination of a simulator model (i.e., the COTSon framework) and a reconfigurable hardware platform (i.e., the AXIOM-board). The AXIOM platform consists of a custom board based on the Xilinx Zynq Ultrascale+ ZU9EG, which incorporates the largest FPGA available on that System-on-Chip at the moment, four 64-bit ARM cores and two 32-bit ARM cores, up to 32GiB of main memory and several 16Gbit/s transceivers.While a complete DF-Threads system is still under development, but is already capable of running a full Linux OS and simple applications, so some initial results are presented here. In particular, well-known programming models that are used to exploit the Thread-Level Parallelism such as Cilk, OpenMPI and Jump are compared with DF-thread execution. Cilk is good for multi-cores, but it is not suitable for multi-nodes systems. In the latter cases, the distribution of the workload could be managed partly by the programmer when using programming models such as message-passing (OpenMPI has been chosen for reference) or distributed shared-memory (Jump in our case).The obtained results show that a DF-Thread execution on a cluster of eight 4-core boards can provide a speed-up of more than 14x compared to the same configuration when using OpenMPI and more than 80x when compared with a OpenMPI single core, single node execution.

Modeling, simulation, and implementation issues of CPGs for neuromorphic engineering applications

AbstractNeuromorphic engineering is a discipline used to develop hardware, which can mimic the characteristics and abilities of biological systems by investigating their physiological structures and data transfer mechanisms. The recent studies about the neuromorphic systems mostly consist of robotic applications whose designs are inspired by Central Pattern Generators (CPGs). CPGs are special neural networks which can produce coordinated rhythmic activity patterns and these rhythmic movements are modeled mathematically, tested with simulation programs and verified by hardware implementations. A reconfigurable hardware platform (Field Programmable Gate Array “FPGA”) is compatible with numerical simulation tools, allows software control over hardware, has a user‐friendly interface and allows real time modifications. Thus, recently, it is preferred in CPG based robotic applications. In this study, the details of the modeling, simulation and implementation stages of several CPG structures are introduced by using a digital reconfigurable hardware platform. In order to show the conceptual learning achievements of these stages and to assess the contribution to the modeling, simulation and implementation skills of the students, a training course has been planned for the undergraduate students at Erciyes University. This process has been held in an educative manner supported by a survey and an experimental examination, so that this training course has been evaluated by the trainees in terms of the advantage, practicality, and challenge.

Energy and Delay Optimization of Heterogeneous Multicore Wireless Multimedia Sensor Nodes by Adaptive Genetic‐Simulated Annealing Algorithm

Energy efficiency and delay optimization are significant for the proliferation of wireless multimedia sensor network (WMSN). In this article, an energy‐efficient, delay‐efficient, hardware and software cooptimization platform is researched to minimize the energy cost while guaranteeing the deadline of the real‐time WMSN tasks. First, a multicore reconfigurable WMSN hardware platform is designed and implemented. This platform uses both the heterogeneous multicore architecture and the dynamic voltage and frequency scaling (DVFS) technique. By this means, the nodes can adjust the hardware characteristics dynamically in terms of the software run‐time contexts. Consequently, the software can be executed more efficiently with less energy cost and shorter execution time. Then, based on this hardware platform, an energy and delay multiobjective optimization algorithm and a DVFS adaption algorithm are investigated. These algorithms aim to search out the global energy optimization solution within the acceptable calculation time and strip the time redundancy in the task executing process. Thus, the energy efficiency of the WMSN node can be improved significantly even under strict constraint of the execution time. Simulation and real‐world experiments proved that the proposed approaches can decrease the energy cost by more than 29% compared to the traditional single‐core WMSN node. Moreover, the node can react quickly to the time‐sensitive events.