Reconfigurable Hardware Accelerator Research Articles

S2RNN: Self-Supervised Reconfigurable Neural Network Hardware Accelerator for Machine Learning Applications

S2RNN: Self-Supervised Reconfigurable Neural Network Hardware Accelerator for Machine Learning Applications

Dynamically reconfigurable variable-precision sparse-dense matrix acceleration in Tensorflow Lite

In this paper, we present a dynamically reconfigurable hardware accelerator called FADES (Fused Architecture for DEnse and Sparse matrices). The FADES design offers multiple configuration options that trade off parallelism and complexity using a dataflow model to create four stages that read, compute, scale and write results. FADES is mapped to the programmable logic (PL) and integrated with the TensorFlow Lite inference engine running on the processing system (PS) of a heterogeneous SoC device. The accelerator is used to compute the tensor operations, while the dynamically reconfigurable approach can be used to switch precision between int8 and float modes. This dynamic reconfiguration enables better performance by allowing more cores to be mapped to the resource-constrained device and lower power consumption compared with supporting both arithmetic precisions simultaneously. We compare the proposed hardware with a high-performance systolic architecture for dense matrices obtaining 25% better performance in dense mode with half the DSP blocks in the same technology. In sparse mode, we show that the core can outperform dense mode even at low sparsity levels, and a single-core achieves up to 20x acceleration over the software-optimized NEON RUY library.

Computer Vision-Based Kidney’s (HK-2) Damaged Cells Classification with Reconfigurable Hardware Accelerator (FPGA)

In medical and health sciences, the detection of cell injury plays an important role in diagnosis, personal treatment and disease prevention. Despite recent advancements in tools and methods for image classification, it is challenging to classify cell images with higher precision and accuracy. Cell classification based on computer vision offers significant benefits in biomedicine and healthcare. There have been studies reported where cell classification techniques have been complemented by Artificial Intelligence-based classifiers such as Convolutional Neural Networks. These classifiers suffer from the drawback of the scale of computational resources required for training and hence do not offer real-time classification capabilities for an embedded system platform. Field Programmable Gate Arrays (FPGAs) offer the flexibility of hardware reconfiguration and have emerged as a viable platform for algorithm acceleration. Given that the logic resources and on-chip memory available on a single device are still limited, hardware/software co-design is proposed where image pre-processing and network training were performed in software, and trained architectures were mapped onto an FPGA device (Nexys4DDR) for real-time cell classification. This paper demonstrates that the embedded hardware-based cell classifier performs with almost 100% accuracy in detecting different types of damaged kidney cells.

Universal Reconfigurable Hardware Accelerator for Sparse Machine Learning Predictive Models

This study presents a universal reconfigurable hardware accelerator for efficient processing of sparse decision trees, artificial neural networks and support vector machines. The main idea is to develop a hardware accelerator that will be able to directly process sparse machine learning models, resulting in shorter inference times and lower power consumption compared to existing solutions. To the author’s best knowledge, this is the first hardware accelerator of this type. Additionally, this is the first accelerator that is capable of processing sparse machine learning models of different types. Besides the hardware accelerator itself, algorithms for induction of sparse decision trees, pruning of support vector machines and artificial neural networks are presented. Such sparse machine learning classifiers are attractive since they require significantly less memory resources for storing model parameters. This results in reduced data movement between the accelerator and the DRAM memory, as well as a reduced number of operations required to process input instances, leading to faster and more energy-efficient processing. This could be of a significant interest in edge-based applications, with severely constrained memory, computation resources and power consumption. The performance of algorithms and the developed hardware accelerator are demonstrated using standard benchmark datasets from the UCI Machine Learning Repository database. The results of the experimental study reveal that the proposed algorithms and presented hardware accelerator are superior when compared to some of the existing solutions. Throughput is increased up to 2 times for decision trees, 2.3 times for support vector machines and 38 times for artificial neural networks. When the processing latency is considered, maximum performance improvement is even higher: up to a 4.4 times reduction for decision trees, a 84.1 times reduction for support vector machines and a 22.2 times reduction for artificial neural networks. Finally, since it is capable of supporting sparse classifiers, the usage of the proposed hardware accelerator leads to a significant reduction in energy spent on DRAM data transfers and a reduction of 50.16% for decision trees, 93.65% for support vector machines and as much as 93.75% for artificial neural networks, respectively.

A Flexible and Efficient FPGA Accelerator for Various Large-Scale and Lightweight CNNs

To enable efficient deployment of convolutional neural networks (CNNs) on embedded platforms for different computer vision applications, several convolution variants have been introduced, such as depthwise convolution (DWCV), transposed convolution (TPCV), and dilated convolution (DLCV). To address the utilization degradation issue occurred in a general convolution engine for these emerging operators, a highly flexible and reconfigurable hardware accelerator is proposed to efficiently support various CNN-based vision tasks. Firstly, to avoid workload imbalance of TPCV, a zero transfer and skipping (ZTS) method is proposed to reorganize the computation process. To eliminate the redundant zero calculations of TPCV and DLCV, a sparsity-alike processing (SAP) method is proposed based on weight-oriented dataflow. Secondly, the DWCV or pooling layers are configured to be directly executed after standard convolutions without external memory accesses. Furthermore, a programmable execution schedule is introduced to gain better flexibility. Finally, the proposed accelerator is evaluated on Intel Arria 10 SoC FPGA. Experimental results show state-of-the-art performance on both large-scale and lightweight CNNs for image segmentation or classification. Specifically, the accelerator can achieve a processing speed up to 339.9 FPS and computational efficiency up to 0.58 GOPS/DSP, which is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.3\times $ </tex-math></inline-formula> better than the prior art evaluated on the same network.

Design of Flexible Hardware Accelerators for Image Convolutions and Transposed Convolutions.

Nowadays, computer vision relies heavily on convolutional neural networks (CNNs) to perform complex and accurate tasks. Among them, super-resolution CNNs represent a meaningful example, due to the presence of both convolutional (CONV) and transposed convolutional (TCONV) layers. While the former exploit multiply-and-accumulate (MAC) operations to extract features of interest from incoming feature maps (fmaps), the latter perform MACs to tune the spatial resolution of the received fmaps properly. The ever-growing real-time and low-power requirements of modern computer vision applications represent a stimulus for the research community to investigate the deployment of CNNs on well-suited hardware platforms, such as field programmable gate arrays (FPGAs). FPGAs are widely recognized as valid candidates for trading off computational speed and power consumption, thanks to their flexibility and their capability to also deal with computationally intensive models. In order to reduce the number of operations to be performed, this paper presents a novel hardware-oriented algorithm able to efficiently accelerate both CONVs and TCONVs. The proposed strategy was validated by employing it within a reconfigurable hardware accelerator purposely designed to adapt itself to different operating modes set at run-time. When characterized using the Xilinx XC7K410T FPGA device, the proposed accelerator achieved a throughput of up to 2022.2 GOPS and, in comparison to state-of-the-art competitors, it reached an energy efficiency up to 2.3 times higher, without compromising the overall accuracy.

Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators

With the diffusion of cyber-physical systems and internet of things, adaptivity and low power consumption became of primary importance in digital systems design. Reconfigurable heterogeneous platforms seem to be one of the most suitable choices to cope with such challenging context. However, their development and power optimization are not trivial, especially considering hardware acceleration components. On the one hand high level synthesis could simplify the design of such kind of systems, but on the other hand it can limit the positive effects of the adopted power saving techniques. In this work, the mutual impact of different high level synthesis tools and the application of the well known clock gating strategy in the development of reconfigurable accelerators is studied. The aim is to optimize a clock gating application according to the chosen high level synthesis engine and target technology (Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA)). Different levels of application of clock gating are evaluated, including a novel multi level solution. Besides assessing the benefits and drawbacks of the clock gating application at different levels, hints for future design automation of low power reconfigurable accelerators through high level synthesis are also derived.

The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design

Modern embedded and cyber-physical systems require every day more performance, power efficiency and flexibility, to execute several profiles and functionalities targeting the ever growing adaptivity needs and preserving execution efficiency. Such requirements pushed designers towards the adoption of heterogeneous and reconfigurable substrates, which development and management is not that straightforward. Despite acceleration and flexibility are desirable in many domains, the barrier of hardware deployment and operation is still there since specific advanced expertise and skills are needed. Related challenges are effectively tackled by leveraging on automation strategies that in some cases, as in the proposed work, exploit model-based approaches.This paper is focused on the Multi-Dataflow Composer (MDC) tool, that intends to solve issues related to design, optimization and operation of coarse-grain reconfigurable hardware accelerators and their easy adoption in modern heterogeneous substrates. MDC latest features and improvements are introduced in detail and have been assessed on the so far unexplored robotics application field. A multi-profile trajectory generator for a robotic arm is implemented over a Xilinx FPGA board to show in which cases coarse-grain reconfiguration can be applied and which can be the parameters and trade-offs MDC will allow users to play with.

Is OpenCL Driven Reconfigurable Hardware Suitable for Virtualising 5G Infrastructure?

The Open Computing Language (OpenCL) is increasingly adopted for programming processors with reconfigurable hardware acceleration. The 5G telecommunication infrastructure, imposing strong latency constraints on the managed communications, may benefit from OpenCL-designed accelerated processing. This paper presents the first study to evaluate OpenCL hardware acceleration in the context of a 5G base station physical layer. The implementation and optimization process to accelerate the Orthogonal Frequency Division Multiplexing (OFDM) part of the 5G downlink is conducted on a high-end Field Programmable Gate Array (FPGA). We show that the proposed OpenCL implementation complies with the 5G processing timing requirements since the computation time is consistent with the present 5G deployment. However, to be suitable for 5G, the OpenCL platform must improve the data latency transfer between hardware and software. Moreover, a further enhancement for the OpenCL implementation is to improve the code by means of OpenCL optimization techniques. In this way, the performance can be further improved with respect to optimized software on vectorized high-end processors.

Implementation and Experimentation of an Embedded Data Acquisition/Preprocessing System Based on a Hybrid Reconfigurable Hardware Accelerator for Inertial Measurements

The use of microelectromechanical systems' sensors is growing steadily since it is the cheapest way to get information about the inertial state of a moving object. However, preprocessing inertial data using hybrid reconfigurability is challenging. This article is an analysis of the noise generated by a multisensory data acquisition and preprocessing system that has been implemented to interface inertial sensors (particularly accelerometers and gyroscopes). A multichannel reconfigurable voltage attenuator (MRVA) based on the field-programmable analog array, an alternative to classical voltage dividers, has been created to interface the sensors with the field-programmable gate array. This article describes a hardware accelerator implementation of two calibration/denoising processes based on the moving average filters in order to select the best choice for the preparation of inertial measurement units data, where a precision of 99.72% was reached. The MRVA is interfaced via Xilinx analog-to-digital converter, where an intellectual property has been designed for hardware acceleration using Xilinx system generator.

Exploiting Multi-Level Parallelism for Run-Time Adaptive Inverse Kinematics on Heterogeneous MPSoCs

This paper presents a run-time solver for the inverse kinematics of a robotic arm implemented on a heterogeneous Multi-Processor System-on-Chip (MPSoC). The solver has been formulated as an optimization problem, in which two levels of algorithmic parallelism are proposed: i) the Nelder-Mead derivative-free method used as the optimization engine is modified to allow the evaluation of the cost function in multiple vertices simultaneously, ii) the trajectory is divided into non-overlapping segments, in which all the points are solved concurrently. Algorithmic parallelism is supported by a variable number of parallel instances of a custom hardware accelerator, which speeds up the computation of the forward kinematics equations of the robot required during the resolution of the inverse kinematics. This adaptable scheme provides run-time scalability in terms of trajectory accuracy, logic resources, dependability, and execution time. New design methodologies are used to unify the modeling of the software and hardware partitions of the controller while transparently providing adaptability. They are based on the dataflow Model of Computation (MoC), supported by the PREESM prototyping tool. This tool has been extended to support the use of dynamically reconfigurable hardware accelerators implemented using the ARTICo3 framework. The proposal has been validated with a python-based robotic arm simulator. Experimental results show how the proposed parallelism, combined with hardware acceleration, enables the run-time resolution of the trajectory with adaptable performance using a Xilinx Zynq UltraScale+ MPSoC device.

Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips

Due to increased embedded processing requirements, modern SoCs are becoming heterogeneous computing platforms by combining traditional processing units with custom reconfigurable hardware accelerators (HAs) on an FPGA fabric. However, efficiently managing such HAs in an embedded Linux environment involves handling Linux kernel source code and creating custom device drivers specific to a target platform, therefore negatively impacting development costs, portability and time-to-market. To address this issue, we present LEOSoC, a snap-on user-space manager for dynamically reconfigurable SoCs. Using LEOSoC does not require any specific version of the Linux kernel, nor to rebuild a custom driver for each new kernel release. LEOSoC consists of a base hardware system and a software layer which run on SoCs from various vendors. The system identifies the SoC on which it is running and auto-adapts its communication channels to the HAs accordingly. Furthermore, LEOSoC allows applications to partially or completely change the structure of the HAs at runtime without rebooting the system by leveraging the underlying SoC support for dynamic full/partial FPGA reconfiguration. The system has been tested on multiple commercial off the shelf (COTS) boards from different vendors, each one running different versions of Linux, therefore proving the real portability and usability of LEOSoC in a custom industrial design. Finally, we use a cloud detection algorithm for multispectral image processing as a showcase for LEOSoC's capabilities and performance.

Energy Efficiency Evaluation of Dynamic Partial Reconfiguration in Field Programmable Gate Arrays: An Experimental Case Study

Both computational performances and energy efficiency are required for the development of any mobile or embedded information processing system. The Internet of Things (IoT) is the latest evolution of these systems, paving the way for advancements in ubiquitous computing. In a context in which a large amount of data is often analyzed and processed, it is mandatory to adapt node logic and processing capabilities with respect to the available energy resources. This paper investigates under which conditions a partially reconfigurable hardware accelerator can provide energy saving in complex processing tasks. The paper also presents a useful analysis of how the dynamic partial reconfiguration technique can be used to enable energy efficiency in a generic IoT node that exploits a Field Programmable Gate Array (FPGA) device. Furthermore, this work introduces a hardware infrastructure and new energy metrics tailored for the energy efficiency evaluation of the dynamic partial reconfiguration process in embedded FPGA based devices. Exploiting the ability of reconfiguring circuit portions at runtime, the latest generation of FPGAs can be used to foster a better balance between energy consumption and performance. More specifically, the design methodology for the implemented digital signal processing application was adapted for the ZedBoard. To this aim, a case study of a video filtering system is proposed and analyzed by dynamically loading three different hardware filters from the management software running on a Linux-based device. With more details, the presented analytical framework allows for a direct comparison between the energy efficiency of a dynamic partially reconfigurable device and a static non-reconfigurable one. The estimated timing conditions that allow the dynamic partially reconfigurable process to achieve relevant energy efficiency with respect to the corresponding static architecture are also outlined.

Distributed Packet Processing Architecture with Reconfigurable Hardware Accelerators for 100Gbps Forwarding Performance on Virtualized Edge Router

Distributed Packet Processing Architecture with Reconfigurable Hardware Accelerators for 100Gbps Forwarding Performance on Virtualized Edge Router

Energy-Efficient Adaptive Hardware Accelerator for Text Mining Application Kernels

Text mining is a growing field of applications, which enables the analysis of large text data sets using statistical methods. In recent years, exponential increase in the size of these data sets has strained existing systems, requiring more computing power, server hardware, networking interconnects, and power consumption. For practical reasons, this trend cannot continue in the future. Instead, we propose a reconfigurable hardware accelerator designed for text analytics systems, which can simultaneously improve performance and reduce power consumption. Situated near the last level of memory, it mitigates the need for high-bandwidth processor-to-memory connections, instead capitalizing on close data proximity, massively parallel operation, and analytic-inspired functional units to maximize energy efficiency, while remaining flexible to easily map common text analytic kernels. A field-programmable gate array-based emulation framework demonstrates the functional correctness of the system, and a full eight-core accelerator is synthesized for power, area, and delay estimates. The accelerator can achieve two to three orders of magnitude improvement in energy efficiency versus CPU and general-purpose graphics processing unit (GPU) for various text mining kernels. As a case study, we demonstrate how indexing performance of Lucene, a popular text search and analytics platform, can be improved by an average of 70% over CPU and GPU while significantly reducing data transfer energy and latency.

Reconfigurable Custom Functional Unit Generation and Exploitation for Multiple-Issue Processors

Next-generation digital entertainment and mobile communication devices are anticipated to require greater processor performance. To meet these demands, several researchers have attached a reconfigurable hardware accelerator to the base processor core. The reconfigurable hardware accelerator, termed a reconfigurable customized functional unit (RCFU), is usually realized by multiple processing elements (PE) organized in matrix form. The structure of the RCFU is generated from hot operation patterns of specific applications. Other than the RCFU, 'multiple-issue' is another microarchitectural technique to increase the performance. However, the impact of combining both of these approaches in the same design is not yet well understood. This problem motivates us to design RCFU generation and exploitation algorithms for a multiple-issue processor. To allow more operations to execute on the RCFU simultaneously, the proposed generation algorithm merges several data-independent operation patterns to construct the RCFU architecture. To schedule operations on both the RCFU and functional units (FU) of the base processor core simultaneously, the proposed exploitation algorithm presents a model to represent all available computing resources from both the FUs of the base processor and the PEs in the RCFU. Using this model, the RCFU exploitation problem can be considered as an instruction-scheduling problem. Our experiment achieves an average improvement in execution performance of 50% compared with previous efforts.

SAccO: An implementation platform for scalable FPGA accelerators

This paper presents SAccO (Scalable Accelerator platform Osnabrück), a novel framework for implementing data-intensive applications using scalable and portable reconfigurable hardware accelerators. Instead of using expensive “reconfigurable supercomputers”, SAccO is based on standard PCs and PCI-Express extension cards featuring Field-Programmable Gate Arrays (FPGAs) and memory. In our framework, we exploit task-level parallelism by manually partitioning applications into several parallel processes using the SAccO communication API for data streams. This also allows pure software implementations on PCs without FPGA cards. If an FPGA accelerator is present, the same API calls transfer data between the PC’s CPU and the FPGA. Then, the processes implemented in hardware can exploit instruction-level and pipelining parallelism as well. Furthermore, SAccO components follow a set of hardware implementation rules which enable portable and scalable designs. Device specific hardware wrappers hide the FPGA’s and board’s idiosyncrasies from the application developer.SAccO also comprises a new method to automatically select a task’s optimal degree of parallelism on an FPGA for a given hardware platform, i.e. to generate a hardware design which uses the available communication bandwidth between the PC and the FPGA optimally. Experimental results show the feasibility of our approach.

A programmable Soc for Var ious Image Applications Based on Mobile Devices

This paper presents a programmable System-On-a-chip for various embedded applications that need Neural Network computations. The system is fully implemented into Field-Programmable Gate Array (FPGA) based prototyping platform. The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using real image processing applications, such as optical character recognition (OCR) system.

A Multi-Layer Perceptron SoC for Smart Devices

This paper presents a programmable System-On-a-chip for various embedded applications that need Neural Network computations. The system is fully implemented into Field-Programmable Gate Array (FPGA) based prototyping platform. The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using real image processing applications, such as optical character recognition (OCR) system.

Multithreading on reconfigurable hardware: An architectural approach

In this paper, we address the problem of organization and management of threads on a multithreading custom computing machine composed of a General Purpose Processor (GPP) and Reconfigurable Coprocessors. We target higher portability, flexibility, and performance of the prospective design solutions by means of a strictly architectural approach. Our proposal to improve overall system performance is twofold. First, we provide architectural mechanisms to accelerate applications by supporting computationally intensive kernels with reconfigurable hardware accelerators. Second, we propose an infrastructure capable of facilitating thread management. Besides the architectural and microarchitectural extensions of the reconfigurable computing system, we also propose a hierarchical programming model. The model supports balanced and performance efficient SW/HW co-execution of multithreading applications. We demonstrate that our approach provides better performance–portability and performance–flexibility trade-off characteristics compared to other state-of-the-art proposals. The experimental results, based on real applications, suggest average system speedups between 1.2 and 19.6. Based on singlethreaded synthetic benchmark, we achieve average speedup between 8.5 and 129. For multithreaded synthetic benchmark, the achieved average speedup is between 1.3 and 7.3.