Reconfigurable Computing Research Articles

Reconfigurable neuromorphic computing by a microdroplet

Reconfigurable neuromorphic computing by a microdroplet

Grapher: A Reconfigurable Graph Computing Accelerator with Optimized Processing Elements

In recent years, various graph computing architectures have been proposed to process graph data that represent complex dependencies between different objects in the world. The designs of the processing element (PE) in traditional graph computing accelerators are often optimized for specific graph algorithms or tasks, which limits their flexibility in processing different types of graph algorithms, or the parallel configuration that can be supported by their PE arrays is inefficient. To achieve both flexibility and efficiency, this paper proposes Grapher, a reconfigurable graph computing accelerator based on an optimized PE array, efficiently supporting multiple graph algorithms, enhancing parallel computation, and improving adaptability and system performance through dynamic hardware resource configuration. To verify the performance of Grapher, this paper selected six datasets from the Stanford Network Analysis Project (SNAP) database for testing. Compared with the existing typical graph frameworks Ligra, Gemini, and GraphBIG, the processing time for the six datasets using the BFS, CC, and PR algorithms was reduced by up to 39.31%, 35.43%, and 27.67%, respectively. The energy efficiency has also been improved by 1.8× compared to Hitgraph and 4.7× compared to ThunderGP.

Introduction to the Special Issue on Next Generation Pervasive Reconfigurable Computing for High Performance Real Time Applications

Introduction to the Special Issue on Next Generation Pervasive Reconfigurable Computing for High Performance Real Time Applications

Memristors with Tunable Volatility for Reconfigurable Neuromorphic Computing.

Neuromorphic computing promises an energy-efficient alternative to traditional digital processors in handling data-heavy tasks, primarily driven by the development of both volatile (neuronal) and nonvolatile (synaptic) resistive switches or memristors. However, despite their energy efficiency, memristor-based technologies presently lack functional tunability, thus limiting their competitiveness with arbitrarily programmable (general purpose) digital computers. This work introduces a two-terminal bilayer memristor, which can be tuned among neuronal, synaptic, and hybrid behaviors. The varying behaviors are accessed via facile control over the filament formed within the memristor, enabled by the interplay between the two active ionic species (oxygen vacancies and metal cations). This solution is unlike single-species ion migration employed in most other memristors, which makes their behavior difficult to control. By reconfiguring a single crossbar array of hybrid memristors, two different applications that usually require distinct types of devices are demonstrated - reprogrammable heterogeneous reservoir computing and arbitrary non-Euclidean graph networks. Thus, this work outlines a potential path toward functionally reconfigurable postdigital computers.

Self-learning physical reservoir computer.

A self-learning physical reservoir computer is demonstrated using an adaptive oscillator. Whereas physical reservoir computing repurposes the dynamics of a physical system for computation through machine learning, adaptive oscillators can innately learn and store information in plastic dynamic states. The adaptive state(s) can be used directly as physical node(s), but these plastic states can also be used to self-learn the optimal reservoir parameters for more complex tasks requiring virtual nodes from the base oscillator. Both this self-learning property for reconfigurable computing and the morphable logic gate property of the adaptive oscillator make this an ideal candidate for a multipurpose neuromorphic processor.

Si/CuO Heterojunction-Based Photomemristor for Reconfigurable, Non-Volatile, and Self-Powered In-Sensor Computing.

In-sensor computing has attracted considerable interest as a solution for overcoming the energy efficiency and response time limitations of the traditional von Neumann architecture. Recently, emerging memristors based on transition-metal oxides (TMOs) have attracted attention as promising candidates for in-memory computing owing to their tunable conductance, high speed, and low operational energy. However, the poor photoresponse of TMOs presents challenges for integrating sensing and processing units into a single device. This integration is crucial for eliminating the need for a sensor/processor interface and achieving energy-efficient in-sensor computing systems. In this study, a Si/CuO heterojunction-based photomemristor is proposed that combines the reversible resistive switching behavior of CuO with the appropriate optical absorption bandgap of the Si substrate. The proposed photomemristor demonstrates a simultaneous reconfigurable, non-volatile, and self-powered photoresponse, producing a microampere-level photocurrent at zero bias. The controlled migration of oxygen vacancies in CuO result in distinct energy-band bending at the interface, enabling multiple levels of photoresponsivity. Additionally, the device exhibits high stability and ultrafast response speed to the built-in electric field. Furthermore, the prototype photomemristor can be trained to emulate the attention-driven nature of the human visual system, indicating the tremendous potential of TMO-based photomemristors as hardware foundations for in-sensor computing.

A Visionary Look at the Security of Reconfigurable Cloud Computing

A Visionary Look at the Security of Reconfigurable Cloud Computing

Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET.

Single-port ferroelectric FET (FeFET) that performs write and read operations on the same electrical gate prevents its wide application in tunable analog electronics and suffers from read disturb, especially in the high-threshold voltage (VTH) state as the retention energy barrier is reduced by the applied read bias. To address both issues, we propose to adopt a read disturb-free dual-port FeFET where the write is performed on the gate featuring a ferroelectric layer and the read is done on a separate gate featuring a nonferroelectric dielectric. Combining the unique structure and the separate read gate, read disturb is eliminated as the applied field is aligned with polarization in the high-VTH state, thus improving its stability, while it is screened by the channel inversion charge and exerts no negative impact on the low-VTH state stability. Comprehensive theoretical and experimental validation has been performed on fully depleted silicon-on-insulator (FDSOI) FeFETs integrated on a 22 nm platform, which intrinsically has dual ports with its buried oxide layer acting as the nonferroelectric dielectric. Novel applications that can exploit the proposed dual-port FeFET are proposed and experimentally demonstrated for the first time, including FPGA that harnesses its read disturb-free feature and tunable analog electronics (e.g., frequency tunable ring oscillator in this work) leveraging the separated write and read paths.

Reconfigurable Neuromorphic Computing: Materials, Devices, and Integration.

Neuromorphic computing has been attracting ever-increasing attention due to superior energy efficiency, with great promise to promote the next wave of artificial general intelligence in the post-Moore era. Current approaches are, however, broadly designed for stationary and unitary assignments, thus encountering reluctant interconnections, power consumption, and data-intensive computing in that domain. Reconfigurable neuromorphic computing, an on-demand paradigm inspired by the inherent programmability of brain, can maximally reallocate finite resources to perform the proliferation of reproducibly brain-inspired functions, highlighting a disruptive framework for bridging the gap between different primitives. Although relevant research has flourished in diverse materials and devices with novel mechanisms and architectures, a precise overview remains blank and urgently desirable. Herein, the recent strides along this pursuit are systematically reviewed from material, device, and integration perspectives. At the material and device level, one comprehensively conclude the dominant mechanisms for reconfigurability, categorized into ion migration, carrier migration, phase transition, spintronics, and photonics. Integration-level developments for reconfigurable neuromorphic computing are also exhibited. Finally, a perspective on the future challenges for reconfigurable neuromorphic computing is discussed, definitely expanding its horizon for scientific communities.

Demonstration of optically-assisted reconfigurable average of two 20-Gbaud 4-phase-encoded data channels using nonlinear wave mixing.

Networks can play a key role in high-speed and reconfigurable arithmetic computing. However, two performance bottlenecks may arise when: (i) relying solely on electronics to handle computation for multiple data channels at high data rates, and (ii) the data streams input to a processing node (PN) are transmitted as phase-encoded signals over an optical network. We experimentally demonstrate the operation of optically-assisted reconfigurable average of two 4-phase-encoded data channels at 10- and 20-Gbaud rates. Our input signals are two streams of 2-bit numbers representing a binary floating-point format, and the operation results in 7-phase-encoded output signals represented by 3-bit numbers. The average operation is achieved in three stages: (1) phase encoding and division-using an optical modulator to encode the data streams; (2) summation-using a highly nonlinear fiber (HNLF); and (3) multicast-using a periodically poled lithium niobate (PPLN) waveguide to multicast back the result into the original signal wavelengths. The experimental results validate the concept, and the measured penalties indicate that: (i) the error vector magnitudes (EVMs) of optical signals increase at each stage and reach ∼18-21% for the final multicast results, and (ii) compared to the inputs, the optical signal-to-noise ratio (OSNR) penalty of output is ∼6.7 dB for the 10-Gbaud rate and ∼6.9 dB for the 20-Gbaud rate at a bit error rate (BER) of 3.8e-3.

Designing spiking neural networks for robust and reconfigurable computation

Networks of spiking neurons constitute analog systems capable of effective and resilient computing. Recent work has shown that networks of symmetrically connected inhibitory neurons may implement basic computations such that they are resilient to system disruption. For instance, if the functionality of one neuron is lost (e.g., the neuron, along with its connections, is removed), the system may be robustly reconfigured by adapting only one global system parameter. How to effectively adapt network parameters to robustly perform a given computation is still unclear. Here, we present an analytical approach to derive such parameters. Specifically, we analyze k-winners-takes-all (k-WTA) computations, basic computational tasks of identifying the k largest signals from a total of N input signals from which one can construct any computation. We identify and characterize different dynamical regimes and provide analytical expressions for the transitions between different numbers k of winners as a function of both input and network parameters. Our results thereby provide analytical insights about the dynamics underlying k-winner-takes-all functionality as well as an effective way of designing spiking neural network computing systems implementing disruption-resilient dynamics.

Towards Complete and Scalable Emulation of Quantum Algorithms on High-Performance Reconfigurable Computers

Contemporary quantum computers face many critical challenges that limit their usefulness for practical applications. A primary limiting factor is classical-to-quantum (C2Q) data encoding, which requires specific circuits for quantum state initialization. The required state initialization circuits are often complex and violate decoherence constraints, particularly for I/O intensive applications. Existing Noisy Intermediate-Scale Quantum (NISQ) devices are noise-sensitive and have low quantum bit (qubit) counts, thus limiting the applicability of C2Q circuits for encoding large and realistic datasets. This has made the study of complete and realistic circuits that include data encoding challenging and has also led to a heavy dependency on costly and resource-intensive simulations on classical platforms. In this work, we propose a cost-effective, classical-hardware-accelerated framework for realistic and complete emulation of quantum algorithms. The emulation framework incorporates components for the critical C2Q data encoding process, as well as architectures for quantum algorithms such as the quantum Haar transform (QHT). The framework is used to investigate optimizations for C2Q and QHT algorithms, and the corresponding optimized quantum circuits are presented. The framework is implemented on a High-Performance Reconfigurable Computer (HPRC) which emulates the proposed QHT circuits combined with proposed C2Q data encoding methods. For performance benchmarks, CPU-based emulations and simulations on a state-of-the-art quantum computing simulator are also carried out. Results show that the proposed hardware-accelerated emulation framework is more efficient in terms of speed and scalability compared to CPU-based emulation and simulation.

A Case for Low-Cost Personal Electronic Laboratory Equipment using FPGAs

The field of reconfigurable computing is gaining a lot of following, and several use cases have been developed for it. At the centre of reconfigurable computing is the field programmable gate array (FPGA) due to its computational speed and versatility. The goal of the work reported here was to show that a single FPGA board paired with a computer monitor can be used as the sole laboratory equipment in a cash-strapped educational institution or by an individual. A Terasic DE1-SoC board was programmed as an oscilloscope, and digital multimeter. In keeping with the low-cost theme of this work, no external signal conditioning circuit was used and the on-board LTC2308 ADC was used for signal acquisition. At frequencies below 15 kHz, the voltage measurements of the developed FPGA lab instrument had a mean error of 58 mV. The voltage measurement errors, however, increased with an increase in frequency and the errors were significant when the signal frequencies exceeded 100 kHz. In terms of the use of the FPGA to replace multiple lab instruments, 13% of the DSPs on the FPGA were used for the implementation and 80% of the Adaptive logic modules. We therefore demonstrate that with $300 dollars, multiple pieces of laboratory equipment can be replaced by a single FPGA board and a monitor.

New trends in photonic switching and optical networking architectures for data centers and computing systems [Invited

The rapid increases in data traffic coupled with user preferences are driving the data center and computing system service providers to offer energy-efficient, intelligent, flexible, cost-effective, high-capacity, and low-latency data services without added complexity to the users. Disaggregated heterogeneous reconfigurable computing systems realized by photonic switching and interconnects can enhance throughput and energy efficiency for artificial intelligence/machine learning (AI/ML) workloads, especially when aided by the AI/ML-enhanced control plane. Photonic switching and new optical networking architectures are expected to solve many of these challenging problems. This paper discusses new trends in photonic switching and optical network architectures for future data centers and computing systems summarized as follows: (1) flat reconfigurable disaggregated computing enabled by high-radix photonic switching and interconnects in data centers; (2) chiplet-based computing architectures empowered by embedded photonics toward heterogeneous reconfigurable computing; (3) nanosecond-scale photonic switching in data centers and computing systems; (4) AI/ML in self-driving, application-aware, and situation-aware data centers; (5) the emergence of flexible networking for cloud computing, edge computing, and split computing, as well as flexible networking for 5G/6G RF-optical networks; and (6) the deployment of embedded co-designed silicon photonics being considered for future data centers.

Interfacing Biology and Electronics with Memristive Materials.

Memristive technologies promise to have a large impact on modern electronics, particularly in the areas of reconfigurable computing and artificial intelligence (AI) hardware. Meanwhile, the evolution of memristive materials alongside the technological progress is opening application perspectives also in the biomedical field, particularly for implantable and lab-on-a-chip devices where advanced sensing technologies generate a large amount of data. Memristive devices are emerging as bioelectronic links merging biosensing with computation, acting as physical processors of analog signals or in the framework of advanced digital computing architectures. Recent developments in the processing of electrical neural signals, as well as on transduction and processing of chemical biomarkers of neural and endocrine functions, are reviewed. It is concluded with a critical perspective on the future applicability of memristive devices as pivotal building blocks in bio-AI fusion concepts and bionic schemes.

Reliability analysis of core power optimization control using Kalman filter for accelerator driven system based on reconfigurable computing

Accelerator Driven System (ADS) is a promising nuclear facility for the transmutation of minor actinides and long-lived fission products, which is constructed by proton accelerator, spallation target and sub-critical reactor. For the industrial implementation, the reliability of core power control system in the operation process has to be analyzed and verified in considering the dynamic characteristics and real time response for the safety operation strategy. Therefore, a digitalization of Instrumentation and Control (I&C) system for ADS that can predict the changing value of proton beam intensity has been suggested in this research to get the appropriate variation of reactor core power without arousing the unexpected impulse to the main structures. In order to accurately analyze the random behavior of the precursor concentrations and the neutron density in sub-critical reactor, the stochastic differential equation model has been developed, and the closed-loop control system in describing the mapping relationship between the proton beam intensity and the corresponding core power has been established. The Kalman filter has been adopted for the optimal design of proposed analysis method to achieve the competitive predicting performance in operation process, and all the algorithms have been implemented on the XILINX ZYNQ System-on-Chip (SoC) using reconfigurable computing technology to meet the real time design requirements for embedded applications. Finally, the reliability of core power control model has been tested against Monte Carlo calculations and all the results demonstrate the good performance in predicting the core power with acceptable efficiency.

Multiplication Circuit Architecture for Error- Tolerant CNN-Based Keywords Speech Recognition

Approximate multiplication is an emerging circuit design technique for AI-based IoT devices which can reduce the energy consumption. A precision reconfigurable tensor multiplication unit (TMU) is proposed to explore the advantages for energy efficient approximate computing for error-tolerant convolutional neural network (CNN) based keywords speech recognition, which is a widely used human-machine interaction system. A positive-negative encoding method and a reorganization structure of partial products are proposed for the tensor multiplication. The partial products are further optimized by a hierarchical addition tree structure with fine-grained precision reconfigurable approximate computing. The imprecision parts of the addition tree are optimized with a low supply voltage. The effects of circuit configuration variations on accuracy and power consumption have been evaluated under 22nm process technology. The proposed approximate designs are applied to a CNN-based keywords speech recognition system. With the proposed approach, the energy efficiency of the CNN accelerator can be greatly improved with a power reduction of up to 44.1% at a loss in accuracy of less than 2%.

High-Level Synthesis Toolchain "Theseus" for Multichip Reconfigurable Computer Systems

High-Level Synthesis Toolchain "Theseus" for Multichip Reconfigurable Computer Systems

Open-Source Ethernet MAC IP Cores for FPGAs: Overview and Evaluation

Field-Programmable Gate Arrays (FPGAs) can be found in an increasing number of application domains, such as the telecom industry, the automotive electronics sector, or automation technology as well as in the area of reconfigurable computing. In recent years, it can be observed that the open-source idea which is known from the software domain for a long time also became popular in the world of hardware and FPGA design. In the era of the Internet of Things, many of today’s electronic devices implement some kind of network interface with Ethernet being known as one of the most widely used network standards. Thus, there is consequently a high demand on available Ethernet implementations for FPGA platforms. The goal of this work is to survey available open-source Ethernet MAC IP cores, evaluate existing designs in terms of performance, resource utilization, code quality, or maturity, and to present and summarize the evaluation results herein. Furthermore, advantages of commercial solutions and related publication work are discussed. To the authors’ best knowledge, this is the first publication that evaluates and compares existing open-source Ethernet MAC IP cores on a large scale. This work should help designers to select an appropriate open-source Ethernet MAC for an FPGA design and shows possible pitfalls and things to pay attention when using an open-source IP core in general. Finally, the authors would like to show that the open-source community can be also very helpful in the world of hardware in terms of design reuse or time to market.

Autotesting an Embedded Reconfigurable Computing System

Purpose of research. The main idea is to build a mathematical testing model that integrates different aspects of an embedded reconfigurable computing system and its interactions. This model provides an efficient representation of test scenarios and allows to analyse the dynamics of the reconfigurable computing system during testing. The paper also discusses methods for generating test sequences based on the properties of a finite state machine.Methods. The authors propose to represent the autotest as a finite state Mile machine, where states serve to store information about the current state of an embedded reconfigurable computing system. The input signal is the interaction with the system and the output signal is the system's response to the input signal. This approach allows to formalize the testing process and simplify the analysis of possible problems.Results. This paper discusses the application of automata theory in the context of automated testing of embedded reconfigurable computing systems. Automata theory provides effective methods and tools for analysis and simulation of discrete dynamic systems, which makes it suitable for automated testing tasks.Conclusion. The results show that the use of automata theory can significantly improve the quality and efficiency of automated testing of embedded reconfigurable computing systems. This approach provides a deeper analysis of the system and allows to detect and prevent potential problems that may arise during its operation.