Reconfigurable Computing Array Research Articles

ReSSIM: a mixed-level simulator for dynamic coarse-grained reconfigurable processor

This paper proposes a mixed-level simulator for dynamic coarse-grained reconfigurable processor (CGRP), called ReSSIM (reconfigurable system simulation implementation mechanism), and the corresponding simulation tool-chain, including task compiler, profiler and debugger. A generic modeling methodology support- ing convenient extension of on-chip modules is also proposed. In order to explore the details of the interested modules while maintaining reasonable simulation speed, RCA (reconfigurable computing array), the key reconfig- urable device in ReSSIM, is modeled on cycle-accurate level, while the other modules are modeled on transaction level. The typical parameters of RCA are scalable and adjustable, which helps the architects to explore the massive details of the reconfigurable device. Experiment shows that simulation speedup achieved ranges from 9.26× to 18.39× compared with VCS (Synopsys verilog compiler simulator) when running three computing- intensive kernel tasks of H.264 decoding algorithm—IDCT (inverse discrete cosine transform), deblocking and MC-chroma (motion compensation). Simulation speed for a set of real applications, such as MPEG4, G.729 and EFR, is 35× slower than the corresponding native executions (i.e. measured from the real chip). And the relative simulation errors are 11% less than the measured IPC (instructions per cycle) of the real chip.

Cyclic coding algorithms under MorphoSys reconfigurable computing system

This paper introduces reconfigurable computing (RC) and specifically chooses one of the prototypes in this field, MorphoSys (M1) [1–5]. The paper addresses the results obtained when using RC in mapping algorithms pertaining to digital coding in relation to previous research [6–10]. The chosen algorithms relate to cyclic coding techniques, namely the CCITT CRC-16 and the CRC-16. A performance analysis study of the M1 RC system is also presented to evaluate the efficiency of the algorithm execution on the M1 system. For comparison purposes, three other systems were used to map the same algorithms showing the advantages and disadvantages of each compared with the M1 system. The algorithms were run on the 8×8 RC (reconfigurable) array of the M1 (MorphoSys) system; numerical examples were simulated to validate our results, using the MorphoSys mULATE program, which simulates MorphoSys operations.