Reconfigurable Bus System Research Articles

Polylogarithmic Gap between Meshes with Reconfigurable Row/Column Buses and Meshes with Statically Partitioned Buses

This paper studies the difference in computational power between the mesh-connected parallel computers equipped with dynamically reconfigurable bus systems and those with static ones. The mesh with separable buses (MSB) is the mesh-connected parallel computer with dynamically reconfigurable row/column buses. The broadcast buses of the MSB can be dynamically sectioned into smaller bus segments by program control. We show that the MSB of size n×n can work with ?(?log?^2?n ) step even if its dynamic reconfigurable function is disabled. Here, we assume the word-model broadcast buses, and use the relation between the word-model bus and the bit-model bus.

THE TRANSITIVE CLOSURE AND RELATED ALGORITHMS OF DIGRAPH ON THE RECONFIGURABLE ARCHITECTURE

The reconfigurable architecture is a parallel computation model that consists of many processor elements (PEs) and a reconfigurable bus system. There are many variant proposed reconfigurable architectures, for example, reconfigurable mesh (R-Mesh), directional reconfigurable mesh (DR-Mesh), processor arrays with reconfigurable bus systems (PARBS), complete directional processor arrays with reconfigurable bus systems (CD-PARBS), reconfigurable multiple bus machine (RMBM), directional reconfigurable multiple bus machine (directional RMBM), and etc. In this paper, a transitive closure (TC) algorithm of digraph is proposed on the models without the directional capability (non-directional). Some related digraph problems, such as strongly connected digraph, strongly connected component (SCC), cyclic checking, and tree construction, can also be resolved by modifying our transitive closure algorithm. All the proposed algorithms are designed on a three-dimensional (3-D) n×n×n non-directional reconfigurable mesh, n is the number of vertices in a digraph D, and can resolve the respective problems in O(log d(D)) time, d(D) is the diameter of the digraph D. The cyclic checking problem can be further reduced to O(log c(D)) time, c(D) is the minimum distance of cycles in the digraph D. There exist two different approaches: the matrix multiplication approach on the non-directional models for algebraic path problems (APP) and s-t connectivity approach on the directional models. In this paper, we will use the tree construction algorithm to prove those two approaches are insufficient to resolve all digraph problems and demonstrate why our approach is so important and innovative for digraph problems on the reconfigurable models.

Impact of Reconfigurable Function on Meshes with Row/Column Buses

This paper studies the difference in computational power between the mesh-connected parallel computers equipped with dynamically reconfigurable bus systems and those with static ones. The mesh with separable buses (MSB) is the mesh-connected computer with dynamically reconfigurable row/column buses. The broadcasting buses of the MSB can be dynamically sectioned into smaller bus segments by program control. We examine the impact of reconfigurable capability on the computational power of the MSB model, and investigate how computing power of the MSB decreases when we deprive the MSB of its reconfigurability. We show that any single step of the MSB of size n A— n can be simulated in O (log n ) time by the MSB without its reconfigurable function, which means that the MSB of size n A— n can work with O (log n ) step slowdown even if its dynamic reconfigurable function is disabled.

A linear-time algorithm for computing collision-free path on reconfigurable mesh

The reconfigurable mesh (RMESH) is an array of mesh-connected processors equipped with a reconfigurable bus system, which can dynamically connect the processors in various patterns. A 2D reconfigurable mesh can be used to solve motion planning problems in robotics research, in which the 2D image of robot and obstacles are digitized and represented one pixel per processor. In this paper, we present an algorithm to compute a collision-free path between two points in an environment containing obstacles. The time complexity of the algorithm is O ( k ) for each pair of source/destination points, with O ( log 2 N ) preprocessing time, where k is the number of obstacles in the working environment, and N is the size of the reconfigurable mesh.

Work-efficient BSR-based parallel algorithms for some fundamental problems in graph theory

This paper presents BSR-parallel algorithms for some problems in fundamental graph theory : transitive closure, connected components, spanning tree, bridges and articulation points of a graph and bipartite graph recognition. There already exist constant time algorithms to solve these problems on a mesh with reconfigurable bus system using O(N 4) processors. Here we show that these problems can be solved in constant time using only O(N 2) processors on the BSR model (N is the number of vertices of the graph G). Therefore, our algorithms are more work-efficient. These new results suggest that many other problems in graph theory can be solved in constant time using the BSR model.

A dynamic processor management strategy on the reconfigurable meshes

A reconfigurable mesh consists of a mesh connected topology augmented by a dynamically reconfigurable bus system. The reconfigurable mesh combines two attractive features of massively parallel system, namely constant diameter and the flexibility of the bus system. Efficient utilisation of processing resources in a large, multi user parallel system depends on the reliable processor management scheme. This paper presents a dynamic and reliable processor allocation strategy to increase the performance of mesh connected parallel systems with faulty processors. The basic idea is to reconfigure a faulty mesh system into a maximum convex system using the fault free upper or lower boundary nodes to compensate for the nonboundary faulty nodes. To utilise the nonrectangular shaped system parts, our strategy tries to allocate L shaped submeshes instead of signalling the allocation failure. Extensive simulations show that the strategy performs more efficiently than other strategies in terms of the completion time, the job response time and the system utilisation.

Scalable and efficient parallel algorithms for Euclidean distance transform on the LARPBS model

A parallel algorithm for Euclidean distance transform (EDT) on linear array with reconfigurable pipeline bus system (LARPBS) is presented. For an image with n/spl times/n pixels, the algorithm can complete EDT transform in O(n log n/c(n) log d(n)) time using n/spl middot/d(n)/spl middot/c(n) processors, where c(n) and d(n) are parameters satisfying 1/spl les/c(n)/spl les/n, and 1<d(n)/spl les/n, respectively. By selecting different c(n) and d(n), the time complexity and the number of processors used can be adjusted. This makes the algorithm highly scalable and flexible. The algorithm also provides a general framework for EDT algorithms on LARPBS, and many existing and unknown parallel EDT algorithms can be deduced from this framework. In particular, if we let c(n)=n, d(n)=n/sup /spl epsiv//, the algorithm can be completed in O(1) time using n/sup 2+/spl epsiv// processors. To the best of our knowledge, this is the most efficient constant-time EDT algorithm on LARPBS.

A Fast Efficient Parallel Hough Transform Algorithm on LARPBS

A parallel algorithm for Hough transform on a linear array with reconfigurable pipeline bus system (LARPBS) is presented. Suppose the number of θ-values to be considered is m, for an image with n × n pixels, the algorithm can complete Hough transform in O(1) time using mn2 processors and achieve optimal speed and efficiency. We also illustrate how to partition data and perform the algorithm on a LARPBS with fewer than mn2 processors, and hence show that the algorithm is highly scalable.

Efficient Parallel Algorithms for Euclidean Distance Transform

The Euclidean Distance Transform (EDT) converts a binary image into one where each pixel has a value equal to its distance to the nearest foreground pixel. Two parallel algorithms for EDT transform on linear array with reconfigurable pipeline bus system (LARPBS) are presented. For an image with n×n pixels, the first algorithm can complete EDT transform in ) log log log log log log ( n n n O time using n processors. The second algorithm can compute the EDT in O( log n loglog n) time using n n log log 2 processors.

Constant-time Algorithms for Minimum Spanning Tree and Related Problems on Processor Array with Reconfigurable Bus Systems

Constant-time Algorithms for Minimum Spanning Tree and Related Problems on Processor Array with Reconfigurable Bus Systems

Efficient minimum spanning tree algorithms on the reconfigurable mesh

The reconfigurable mesh consists of an array of processors intercon- nected by a reconfigurable bus system. The bus system can be used to dynamically obtain various interconnection patterns among the processors. Recently, this model has attracted a lot of attention. In this paper, two efficient algorithms are proposed for computing the minimum spanning tree of an n-vertex undirected graph. One runs on an n x n reconfigurable mesh with time complexity of O(log 2 n). The other runs with time complexity of O(logn) on an n TM x n reconfigurable mesh, where 0 < e < 1 is a constant. All these improve the previously known results on the reconfigurable mesh.

SORTING AND SELECTION ON A LINEAR ARRAY WITH OPTICAL BUS SYSTEM

In this paper we present randomized algorithms for selection and sorting on linear arrays with optical bus communication systems. We show that sorting n given numbers can be performed in O( log n) time with high probability on a linear array, of n processors, with a reconfigurable optical bus system (Linear-AROB). We also show that selection can be performed in O(1) time with high probability on the same parallel machine model.

Parallel directed graph algorithms on directional processor arrays with reconfigurable bus systems

Processors arrays with reconfigurable bus systems (abbreviated to PARBS) have been received a lot of attention in the last decade, and many undirected graph algorithms with constant time complexity have been proposed on PARBS. However, for a directed graph, it will be proved that connecting PARBS in the way proposed for undirected graphs generates paths which do not exist in the directed graph. This result may lead to incorrect solution for directed graph problems. Therefore, in this paper, a model named D-PARBS (Directional PARBS) is proposed for eliminating the non-existent paths. This model can be used to correctly identifying redundant arcs on directed graphs in constant time. Furthermore, by modifying the D-PARBS architecture, constant time algorithms with O(n3) processors are developed to solve topological sort, transitive closure, cyclic graph checking, and strongly connected component problems on directed graphs.

Optimal Speed-Up Parallel Image Template Matching Algorithms on Processor Arrays with a Reconfigurable Bus System,

The image template matching problem is one of the fundamental problems of and has many practical applications in image processing, pattern recognition, and computer vision. It is a useful operation for filtering, edge detection, image registration, and object detection [13]. In this paper, we first design twoO[(M2/p2)log logM] andO[(M2/p2)+(M/p)log logp] time parallel image template matching algorithms on a 3-D processor array with a reconfigurable bus system usingp2N2processors with each processor containingO(1) andO(M/p) restricted memory for 1 ≤p≤M≤N, respectively, for anN×Ndigital image and anM×Mtemplate. By increasing the number of processors, these two proposed algorithms can be run inO(M2/p2) time for speeding up the time complexity usingp2M1/cN2andp2+1/cN2processors, respectively, wherecis a constant andc≥1. Furthermore, anO(1) time can be also obtained from these two proposed algorithms by usingM2+1/cN2processors. These results improve the best known bounds and achieve both optimal and optimal speed-up in their time and processor complexities.

A constant time string shuffle algorithm on reconfigurable meshes

The string shuffle problem is to verify whether a string, S, of length n can be constructed by arbitrarily interleaving the characters of two other strings of lengths m and n—m (0<m<n) such that the original order of the characters in these two strings is maintained in S. In this paper, we present an O(l) time algorithm for the string shuffle problem on an n×n processor array with reconfigurable bus system (reconfigurable mesh). The previous best parallel algorithm for the string shuffle problem takes O(log2 n) time using O(n 2/log2 n) processors. Our algorithm is simpler and adopts an entirely different approach when compared to the earlier algorithms.

Constant-time algorithms for constrained triangulations on reconfigurable meshes

A number of applications in computer-aided manufacturing, CAD, and computer-aided geometric design ask for triangulating pieces of material with defects. These tasks are known collectively as constrained triangulations. Recently, a powerful architecture called the reconfigurable mesh has been proposed: In essence, a reconfigurable mesh consists of a mesh-connected architecture augmented by a dynamically reconfigurable bus system. The main contribution of this paper is to show that the flexibility of the reconfigurable mesh can be exploited for the purpose of obtaining constant-time algorithms for a number of constrained triangulation problems. These include triangulating a convex planar region containing any constant number of convex holes, triangulating a convex planar region in the presence of a collection of rectangular holes, and triangulating a set of ordered line segments. Specifically with a collection of O(n) such objects as input, our algorithms run in O(1) time on a reconfigurable mesh of size n/spl times/n. To the best of our knowledge, this is the first time constant time solutions to constrained triangulations are reported on this architecture.

Parallel algorithms for generating combinatorial objects on linear processor arrays with reconfigurable bus systems

A bus system whose configuration can be dynamically changed is called reconfigurable bus system. In this paper, parallel algorithms for generating combinations, subsets, and binary trees on linear processor array with reconfigurable bus systems (PARBS) are presented.

Parallel hierarchical clustering algorithms on processor arrays with a reconfigurable bus system

Clustering techniques are usually used in pattern recognition, image segmentation and object detection. Let N be the number of patterns and M be the number of features of each pattern and N _ ̆ M . In this paper, we first design two O(1) time basic operations for concentrating all nonempty data of size N and computing the proximity matrix using N × N and N × N × M processors, respectively. Then, based on these two operations, a constant time parallel hierarchical clustering algorithm is proposed on a 3-D processor array with reconfigurable bus system using N 4 processors. Then, by reducing the number of processors by a factor of N, an O(log 2 N) time algorithm for this problem is also derived. Note that no one had ever obtained a constant time algorithm for this problem on the existing parallel computation models.

Constant time algorithms for computational geometry on the reconfigurable mesh

The reconfigurable mesh consists of an array of processors interconnected by a reconfigurable bus system. The bus system can be used to dynamically obtain various interconnection patterns among the processors. Recently, this model has attracted a lot of attention. The authors show O(1) time solutions to the following computational geometry problems on the reconfigurable mesh: all-pairs nearest neighbors, convex hull, triangulation, two-dimensional maxima, two-set dominance counting, and smallest enclosing box. All these solutions accept N planar points as input and employ an N/spl times/N reconfigurable mesh. The basic scheme employed in the implementations is to recursively find an O(1) time solution. The number of recursion levels and the size of the subproblems at each level of recursion are optimized such that the problem decomposition and the solution to the problem can be obtained in constant time. As a result, they have developed some efficient merge techniques to combine the solutions for subproblems on the reconfigurable mesh. These techniques exploit reconfigurability in nontrivial ways leading to constant time solutions using optimal size of the mesh.

IMAGE TEMPLATE MATCHING ON RECONFIGURABLE MESHES

A mesh-connected computer enhanced by a reconfigurable bus system is referred to as a reconfigurable mesh (RM). Given an n×n grey-scale image and m×m template, in this paper, an O( log m) time parallel algorithm for template matching is presented on a RM with O(m2n2) processors. Suppose the image and template are binary, an O(1) time algorithm is presented on a RM with O(m3n2) processors. Both algorithms are superior to the best known algorithms on RMs.