Reconfigurable Amplifier Research Articles

Low-Noise Multimodal Reconfigurable Sensor Readout Circuit for Voltage/Current/Resistive/Capacitive Microsensors

This paper presents a low-noise reconfigurable sensor readout circuit with a multimodal sensing chain for voltage/current/resistive/capacitive microsensors such that it can interface with a voltage, current, resistive, or capacitive microsensor, and can be reconfigured for a specific sensor application. The multimodal sensor readout circuit consists of a reconfigurable amplifier, programmable gain amplifier (PGA), low-pass filter (LPF), and analog-to-digital converter (ADC). A chopper stabilization technique was implemented in a multi-path operational amplifier to mitigate 1/f noise and offsets. The 1/f noise and offsets were up-converted by a chopper circuit and caused an output ripple. An AC-coupled ripple rejection loop (RRL) was implemented to reduce the output ripple caused by the chopper. When the amplifier was operated in the discrete-time mode, for example, the capacitive-sensing mode, a correlated double sampling (CDS) scheme reduced the low-frequency noise. The readout circuit was designed to use the 0.18-µm complementary metal-oxide-semiconductor (CMOS) process with an active area of 9.61 mm2. The total power consumption was 2.552 mW with a 1.8-V supply voltage. The measured input referred noise in the voltage-sensing mode was 5.25 µVrms from 1 Hz to 200 Hz.

Low-power ASIC suitable for miniaturized wireless EMG systems

Abstract Nowadays, the technology advancements of signal processing, low-voltage low-power circuits and miniaturized circuits have enabled the design of compact, battery-powered, high performance solutions for a wide range of, particularly, biomedical applications. Novel sensors for human biomedical signals are creating new opportunities for low weight wearable devices which allow continuous monitoring together with freedom of movement of the users. This paper presents the design and implementation of a novel miniaturized low-power sensor in integrated circuit (IC) form suitable for wireless electromyogram (EMG) systems. Signal inputs (electrodes) are connected to this application-specific integrated circuit (ASIC). The ASIC consists of several consecutive parts. Signals from electrodes are fed to an instrumentation amplifier (INA) with fixed gain of 50 and filtered by two filters (a low-pass and high-pass filter), which remove useless signals and noise with frequencies below 20 Hz and above 500 Hz. Then signal is amplified by a variable gain amplifier. The INA together with the reconfigurable amplifier provide overall gain of 50, 200, 500 or 1250. The amplified signal is then converted to pulse density modulated (PDM) signal using a 12-bit delta-sigma modulator. The ASIC is fabricated in TSMC0.18 mixed-signal CMOS technology.

A CMOS reconfigurable distributed amplifier employing large-signal MGTR technique

A CMOS reconfigurable distributed amplifier employing large-signal MGTR technique

A power-efficient reconfigurable amplifier with crossed cascode self-biasing

ABSTRACTA low power reconfigurable sensing amplifier for biomedical applications is proposed. Two cascode voltages in a telescopic amplifier are provided by using only one floating gate and a symmetrically cross self-biasing scheme. Complementary differential pairs and floating-gate techniques are employed to attain low electronic noise and bandwidth reconfigurability with low power consumption. To improve linearity in low frequency operation, gate-balanced pseudo resistors are adopted as feedback resistors. The power efficiency is optimised using a 1.8 V supply voltage with 30 nA current consumption in a 100 Hz bandwidth setting. The measured noise efficiency factor (NEF) is 1.88 with integrated input-referred noise. The dynamic range is above 61.7 dB.

Pareto optimization of radar receiver low-noise amplifier source impedance for low noise and high gain

In radar receivers, the low noise amplifier(LNA)must provide very low noise figure and high gain to successfully receive very low signals reflected off of illuminated targets. Obtaining low noise figure and high gain, unfortunately, is a well-known trade-off that has been carefully negotiated by design engineers for years. This paper presents a fundamental solution method for the source reflection coefficient providing the maximum available gain under a given noise figure constraint, and also for the lowest possible noise figure under a gain constraint. The design approach is based solely on the small-signal S-parameters and noise parameters of the device; no additional measurements or information are required. This method is demonstrated through examples. The results are expected to find application in design of LNAs and in real-time reconfigurable amplifiers for microwave communication and radar receivers.

An ultra-low-power reconfigurable two-stage OTA with improved transconductance and DC gain

ABSTRACTAn ultra-low-power reconfigurable bulk-driven two-stage operational transconductance amplifier (OTA) with enhanced transconductance and dc gain is presented in this article. By means of the partial positive-feedback technique, the effective bulk transconductance of the input stage is improved. Also, the proposed composite-transistor is used to enhance the dc gain of the OTA. In addition, a proposed pseudo-cascode compensation technique to improve the stability of the two-stage OTA in ultra-low-voltage condition, which makes the OTA reconfigurable, is introduced. Transistor-level simulations in UMC 0.18m CMOS process confirm the theoretical results. Simulated from a 0.5-V supply voltage, the proposed OTA achieves a 98 dB dc gain, a 15.5kHz gain-bandwidth and the phase margin varies less than 6% as the bias current scaled by a factor of 200. The power of the proposed OTA is only 38nW.

Reconfigurable matching networks for RF amplifiers

This article presents applications of reconfigurable matching networks for RF amplifier design. Two possible solutions are given, one where the switching element is a PIN diode, and the other is based on graphene. Due to the fact that its conductivity depends on applied bias voltage, the graphene-based circuits can be used in microwave circuits as controllable elements. The structure of the proposed switch is very simple and it is particularly convenient for microstrip-based circuits. Because of that, a design of reconfigurable amplifier with the graphene-based switch is presented together with the one which has the PIN diode switch. Both amplifiers have the same specifications, and the one with the PIN diode switch is fabricated. The amplifier utilizing the PIN switch was used as a reference to make a comparison the two types of switches. Results of both amplifiers are very similar which indicates possible future applications of the graphene-based switch.

Electronically Tunable Doherty Power Amplifier for Multi-Mode Multi-Band Base Stations

This paper proposes an electronically reconfigurable Doherty amplifier capable of efficiently amplifying multi-standard multi-band wireless signals centered at widely spaced frequencies. The paper outlines closed form equations for an effective design methodology of frequency agile Doherty amplifiers driven with multi-mode signals using a small number of electronically tunable devices. As a proof of concept, a reconfigurable Doherty prototype is designed and fabricated to operate at 1.9, 2.14, and 2.6 GHz meant to efficiently amplify signals with peak-to-average power ratio equal to 6, 9 and 12 dB. The measurement results obtained using continuous wave signals reveal drain efficiencies of about 67% and 42% at the peak power and 12 dB output back off power respectively for the three operating frequencies. In addition, the reconfigurable Doherty amplifier is successfully linearized when driven with 20 MHz wideband code-division multiple access and 20 MHz long term evolution signals, using a Volterra based digital predistrtion algorithm which exploits a pruned Volterra series.

Doherty Power Amplifier With Enhanced Efficiency at Extended Operating Average Power Levels

This paper proposes an electronically reconfigurable Doherty amplifier capable of efficiently amplifying wireless signals with significant time varying average power. This paper outlines closed-form equations used to design an effective Doherty amplifier that can be driven with signals of variable power levels using a small number of electronically tunable devices. As a proof of concept, a reconfigurable Doherty amplifier prototype was designed and fabricated that efficiently amplified signals centered at 2.6 GHz with output average power levels equal to 35, 30, and 25 dBm. The measurement results obtained using continuous wave signals revealed power-added efficiencies of greater than 66%, at input power level adjustments of 21 and 16 dBm, and more than 62% when the average input power level setting was adjusted to 11 dBm. In addition, the reconfigurable Doherty amplifier, driven with a 20-MHz long-term evolution signal, was successfully linearized using a pruned Volterra series based digital predistrtion algorithm.

Realization of a 30-W highly efficient and linear reconfigurable dual-band power amplifier using the continuous mode approach

This paper presents the design methodology and the realization of a highly linear and power-efficient reconfigurable dual-band amplifier based on the continuous/Class-ABJ approach. The Class-ABJ theory allows presenting different reactive solutions on both fundamental and second harmonic terminations compared with the standard Class-AB mode. Despite the various terminations, a constant optimum output performance in terms of power, gain, and efficiency can still be achieved. The output impedances are then translated into frequency thus allowing the realization of broadbandpower amplifiers(PAs) at high-power level of 30 W. In this work, the Class-ABJ broadband approach will be used for the realization of a reconfigurable dual-band power amplifier operating in the two frequency bands 2.1–2.2 and 2.5–2.6 GHz. Continuous wave (CW) measurements on the realized PA show power and efficiency greater than 17 W and 55% in the two frequency bands with peak values up to 30 W and 63.7%. Indeed, it is shown that such novel modes can be predistorted and therefore the linearity requirement can also be met.

Reconfigurable Doherty Power Amplifier for Multifrequency Wireless Radio Systems

This paper proposes a frequency-agile Doherty amplifier capable of efficiently amplifying multiband wireless signals located at widely spaced frequencies. Starting with the study of the load modulation concept in the Doherty technique and the various frequency-dependent components involved in its realization, this paper suggests a simplified and effective design methodology for the development of frequency-agile and reconfigurable Doherty amplifiers using a small number of electronically tunable devices. As a proof of concept, a reconfigurable Doherty power amplifier (PA) prototype is designed and fabricated to operate at 1.9, 2.14, and 2.6 GHz. The measurement results obtained using a continuous-wave signal revealed drain efficiencies of approximately 70% and 60% at the peak power and 6 dB back-off power, respectively, for the three targeted operating frequencies. In addition, the reconfigurable Doherty amplifier was successfully linearized when driven with 20-MHz wavelength code-division multiple access and longterm evolution signals, using a Volterra-based digital predistrtion algorithm which exploits a pruned Volterra series.

An Adaptive Amplifier System for Wireless Sensor Network Applications

This paper presents an adaptive amplifier that is part of a sensor node in a wireless sensor network. The system presents a target gain that has to be maintained without direct human intervention despite the presence of faults. In addition, its bandwidth must be as large as possible. The system is composed of a software‐based built‐in self‐test scheme implemented in the node that checks all the available gains in the amplifiers, a reconfigurable amplifier, and a genetic algorithm (GA) for reconfiguring the node resources that runs on a host computer. We adopt a PSoC device from Cypress for the node implementation. The performance evaluation of the scheme presented is made by adopting four different types of fault models in the amplifier gains. The fault simulation results show that GA finds the target gain with low error, maintains the bandwidth above the minimum tolerable bandwidth, and presents a runtime lower than exhaustive search method.

Analysis and Design of Tunable Amplifiers for Implantable Neural Recording Applications

In this paper, an in-depth design methodology for fully-integrated tunable low-noise amplifiers for neural recording applications is presented. In this methodology, a modified system design is proposed to optimize the area/noise/linearity performance. A novel linear pseudo-resistor with a wide range of tunability is also proposed. As a case study, a low-noise tunable and reconfigurable amplifier for neural recording applications is designed and simulated in a 0.18 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\rm m}$</tex> </formula> complementary metal–oxide–semiconductor process in all process corners. Simulated characteristics of the amplifier include tunable gain of 54 dB, tunable high-cutoff frequency of 10 kHz, programmable low-cutoff frequency ranging from 4 to 300 Hz, and power consumption of 20.8 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\rm W}$</tex></formula> at 1.8 V. According to postlayout simulations, integrated input-referred noise of the amplifier is 2.6 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\rm V}_{\rm rms}$</tex></formula> and 2.38 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\rm V}_{\rm rms}$</tex></formula> over the 0.5 Hz–50 kHz frequency range for low-cutoff frequency of 4 and 300 Hz, respectively. The amplifier also provides output voltage swing of 1 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">${\rm V}_{\rm P-P}$</tex></formula> with total harmonic distortion of -46.24 dB at 300 Hz, and -45.97 dB at 10 kHz.

Microresonators in CMOS Compatible Substrate

We report our recent progress in designing and developing traveling-wave microresonators on CMOS compatible substrate, with a focus on ultra-compact Si-based microring and microdisk resonators in the visible and near infrared wavelengths with ultra-high Q and small mode volume, suitable for strong light-matter interaction. The performance of these resonators is discussed, and the design and fabrication challenges and solutions to achieve efficient coupling from the bus-waveguide to the resonator is mentioned. Coupled-resonator architectures for the design of filters are analyzed and theoretical and experimental results for the flat-band filters with wide bandwidth and large free spectral range are presented. Furthermore, by using a detailed thermal model we demonstrate optimized microresonator structures on semiconductor substrates with improved thermal conductivity that can sustain a high circulating optical intensity at the resonance wavelength, which is particularly useful for nonlinear optics and optical signal processing applications. Finally, we address some of the applications and future prospects of such microresonators in CMOS-compatible substrate technology, including portable multi-purpose bio/chemical sensing systems, reconfigurable optical signal processing modules and chip-scale optical amplifiers and lasers.

Towards a generic operational amplifier with dynamic reconfiguration capability

Abstract. Analog and analog-digital mixed signal electronics needed for sensor systems are indispensable components which tend to drifts from the normal phase of operation due to the impact of manufacturing conditions and environmental influences like etching, aging etc. Precise design methodology, trimming / calibration are essential to restore functionality of the system. Recent block level granular approaches using Field Programmable Analog Array and the more recent approaches from evolutionary electronics providing transistor level granularity using Field Programmable Transistor Arrays offers considerable extensions. In our work, we started on a new medium granular level approach called Field Programmable medium-granular Mixed-signal Array (FPMA) providing basic building blocks of heterogeneous array of active and passive devices to configure established circuit structures which are adaptive, biologically inspired and dynamically re-configurable. Our design objective is to create components of clear compatibility to that of the industrial standards having predictable behavior along with the incorporation of existing design knowledge. The cells can be used in as a single instance or multiple instances. Further, we will focus on a generic dynamic reconfigurable amplifier cell with flexible topology and dimension called Generic Operational Amplifier (GOPA). The incentive of our work comes from recent development in the field of measurement and instrumentation. The digital programming of analog devices is carried out using range of algorithms from simple to evolutionary. Physical realization of the basic cells is carried out in 0.35 μm CMOS technology.

A 2.4-GHz dual-mode 0.18-/spl mu/m CMOS transceiver for Bluetooth and 802.11b

High-level integration of the Bluetooth and 802.11b WLAN radio systems in the 2.4-GHz ISM band is demonstrated in scaled CMOS. A dual-mode RF transceiver IC implements all transmit and receive functions including the low-noise amplifier (LNA), 0-dBm power amplifier, up/down mixers, synthesizers, channel filtering, and limiting/automatic gain control for both standards in a single chip without doubling the required silicon area to reduce the combined system cost. This is achieved by sharing the frequency up/down conversion circuits in the RF section and performing the required baseband channel filtering and gain functions with just one set of reconfigurable channel filter and amplifier for both modes. A chip implemented in 0.18-/spl mu/m CMOS occupies 4/spl times/4 mm/sup 2/ including pad and consumes 60 and 40 mA for RX and TX modes, respectively. The dual-mode receiver exhibits -80-dBm sensitivity at 0.1% BER in Bluetooth mode and at 12-dB SNR in WLAN mode.

A MEMS reconfigurable matching network for a class AB amplifier

This letter presents the design of a reconfigurable amplifier with an adaptive matching network implemented by shunt MEMS switches. In particular, the MEMS switches are used as capacitive stubs in double-stub matching circuit designs. The effective capacitance of the switches can be varied by switch activation which results in a change of the matching configuration. The RF response of the adaptive matching network is studied and the power performance of the amplifier is presented.

A reconfigurable audio power amplifier delivering 150 W to 1 Ω loudspeakers for in-car sound systems

A reconfigurable audio amplifier is proposed. It can be configured to operate as a standard dual-bridge, a high-efficiency dual-bridge, or a high-power mono-bridge amplifier. Moreover, all these configurations can be set in low-noise mode. Built-in diagnostics with an I/sup 2/C-bus interface completes the features. The device, realized in a 0.6 /spl mu/m technology, delivers to 1 /spl Omega/ up to 150 W in high-power mode, saves 50% of the dissipated power in the high-efficiency configuration, and has a 16 /spl mu/V RMS in-band output noise in the low-noise configuration.