Realization Of Digital Filters Research Articles

On the minimization of multiplier-adders for powers-of-two filter using a novel right to left (R2L) algorithm

The field of digital signal processing has been receiving increasing attention over the years because of its widespread applications in various fields of science, engineering and technology. In connection to this, design of finite impulse response (FIR) filter has drawn enough attention of researchers throughout the globe. A number of promising developments has been carried out over the last few decades which emphasize on the design of hardware efficient filter structure. In this work, one novel Right to Left (R2L) algorithm is proposed which can minimize the number of multiplier-adders for the powers-of-two FIR filter. The requirement of such adders essentially depends upon the number of such non-zero entries and the word-length of the input signal. Comparative study has been performed amongst few such hardware efficient realizations of digital filters. Finally, the proposed approach has been implemented using Xilinx Plan Ahead 14.7 so as to have a clear understanding about the requirement of different hardware blocks on a field programmable device.

Criterion for the Global Asymptotic Stability of Fixed-Point Lipschitz Nonlinear Digital Filter with 2’s Complement Overflow Arithmetic

This paper is concerned with the global asymptotic stability (GAS) problem of fixed-point Lipschitz nonlinear digital filters employing 2’s complement overflow arithmetic. Nonlinear digital filtering finds immense applications in various fields such as adaptive systems and controllers, digital controllers and observers for nonlinear systems, realization of neural networks using digital hardware, controllers for feedback linearization, etc. Lipschitz nonlinear digital filter is considered in this paper as it is frequently employed in nonlinear digital filtering, state filtering, neural networks, feedback control, digital controllers, decision-taking systems and so on. Based on Lyapunov theory, the property of 2’s complement overflow arithmetic and Lipschitz condition associated with system nonlinearities, a new criterion for the suppression of overflow oscillations in 2’s complement state variable realizations of digital filters is established. Several examples along with simulation results are provided to highlight the utility of the criterion.

Adaptive Normal State-Space Notch Digital Filters: Algorithm and Frequency-Estimation Bias Analysis

This paper investigates an adaptive notch digital filter that employs normal state-space realization of a single-frequency second-order IIR notch digital filter. An adaptive algorithm is developed to minimize the mean-squared output error of the filter iteratively. This algorithm is based on a simplified form of the gradient-decent method. Stability and frequency estimation bias are analyzed for the adaptive iterative algorithm. Finally, a numerical example is presented to demonstrate the validity and effectiveness of the proposed adaptive notch digital filter and the frequency-estimation bias analyzed for the adaptive iterative algorithm.

Hardware Emulation of a Biorthogonal Wavelet Transform-Based Heart Rate Monitoring Device

In this work, a low-power, area-efficient, and high-performance electrocardiogram (ECG) detector that can be used in modern implantable cardiac pacemaker systems is proposed. Qualitative and quantitative analysis indicates that the Biorthogonal-3.1 wavelet transform combined with adaptive slope prediction is best suited to detect various ECG peaks by effectively denoising various artifacts present in an ECG signal. A demand-based wavelet filter bank (WFB) architecture consisting of a series combination of three lowpass filters is the primary reason for the low-power requirements of the circuit. Power consumption and area requirements of the circuit are further reduced by realizing the lowpass filters using lattice wave digital filter realization that reduces the requirement of delay elements, and multipliers count by 80% and 75%, respectively. The proposed ECG denoising scheme using the biorthogonal 3.1 wavelet transform generates a smoother denoised ECG wave by retaining the important morphology of an ECG signal. Adaptive slope prediction criterion-based ECG processing and detection schemes achieve a high detection accuracy of 99.90%, with the lowest error of 0.002%. The proposed scheme is capable of distinguishing between a normal ECG, paced ECG, arrhythmic ECG, and low and high-resolution ECG. The proposed algorithm is then emulated on the Xilinx Ⓡ-Virtex Ⓡ-7 FPGA hardware platform. Power consumption, area, delay, and switching energy of the proposed ECG processing scheme are reduced when compared to existing ECG detection schemes and are found to be of $0.493~\mu \text{W}$ , 1.1 mm2, 10 ns, and $4.93~\mu \text{J}$ , respectively.

Narrow Band Digital Filter for Carrier Aggregation

Digital signal processing takes its place in the field of research as digital systems are taking over the world. The digital filters form the important part of any digital system. Digital filter realizations are improving each day. Commonly designed digital filters use higher order of filter to achieve narrow transition band. One of the applications of narrow transition band filters may be for the user equipment (UE) that uses LTE-Advanced (long Term Evolution) technology. Carrier Aggregation is one among the significant mechanisms of LTE-Advanced. It provides for the wide bandwidth so that the capacity can be increased. Narrow band filters may be used for extracting the desired signal from this wide bandwidth. This paper explores the narrow band FIR filters with the introduction of the small transition band

Overflow oscillations free implementation of state-delayed digital filter with saturation arithmetic and external disturbance

This paper presents a sufficient condition for exponential stability and confirms [Formula: see text] performance of state-delayed digital filters in the simultaneous existence of saturation arithmetic and external disturbance. The realization of limit-cycle free state-space digital filters is carried out by utilizing better characterization of saturation nonlinearities. The presented criterion not only ensures exponential stability but also reduces effect of external interference to a specific attenuation level. The obtained condition is in linear matrix inequality framework, so it is easily tractable. It is also shown that many results reported in literature may be retrieved as a special case from the proposed condition. With the help of numerical examples, it is shown that the presented approach provides enhanced stability region for the digital filters as compared to an existing criterion appeared in literature.

A parallel arithmetic for hardware realization of digital filters

Distributed Arithmetic (DA) is a classic technique for the hardware realization of digital filters. We present a novel parallel arithmetic operation to overcome two drawbacks in existing DA and DA-based methods: 1) the throughput is difficult to improve and 2) hardware resource consumption increases exponentially with the length of filter order. The fundamental difference between the proposed and existing methods is that the proposed method factors the filter coefficients to find several simple basic operations, which can circumvent the inherent bit-serial nature of DA methods and achieve the whole operation in one clock cycle. Additionally, the number of possible basic operations increases linearly with the length of filter order, which means we can relieve the exponentially increasing hardware resource consumption. The proposed method is evaluated through two experiments, and the results demonstrate that the proposed technique outperforms existing DA and DA-based methods in terms of throughput and resource consumption.

REALIZATION OF DIGITAL FILTERS WITH COMPLEX COEFFICIENTS

A comprehensive analysis of realization of digital filters with complex coefficients obtained by decomposition of real digital filters, using complex and real allpass networks, is given in the paper. Realization of complex coefficient filters obtained directly in the z domain is also discussed in the paper. An analysis of hardware costs for different structures used for realization of complex coefficient filters is presented.

Generalized Wave Digital Filter Realizations of Arbitrary Reciprocal Connection Networks

In this paper, an existing approach for modeling and efficiently implementing arbitrary reciprocal connection networks using wave digital (WD) scattering junctions based on voltage waves is extended to be used in a broader class of WD filters (WDFs) based on different kinds of waves. A generalized wave definition which includes traditional voltage waves, current waves, and power-normalized waves as particular cases is employed. Closed-form formulas for computing the scattering matrices of the junctions are provided. Moreover, the approach is also extended to the family of Biparametric WDFs, which have been recently introduced in the literature.

Overflow oscillation-free realization of digital filters with saturation

PurposeThe purpose of this paper is to establish a criterion for the global asymptotic stability of fixed-point state–space digital filters using saturation overflow arithmetic.Design/methodology/approachThe method of stability analysis used in this paper is the second method of Lyapunov. The approach in this paper makes use of a precise upper bound of the state vector of the system and a novel passivity property associated with the saturation nonlinearities.FindingsThe presented criterion leads to an enhanced stability region in the parameter-space as compared to several existing criteria.Practical implicationsWhen dealing with the design of fixed-point state–space digital filters, it is desirable to have a criterion for selecting the filter coefficients so that the designed filter becomes free of overflow oscillations. The criterion presented in this paper provides enhanced saturation overflow stability region and therefore facilitates the designer greater flexibility in selecting filter parameters for overflow oscillation-free realization of digital filters.Originality/valueThe approach uses the structural properties of the saturation nonlinearities in a greater detail. The exploitation of upper bound of the system state vector together with a new passivity property of saturation nonlinearities is a unique feature of the present approach. The presented approach may lead to results not covered by several existing approaches.

ISS Criterion for the Realization of Fixed-Point State-Space Digital Filters with Saturation Arithmetic and External Interference

This paper investigates the problem of the input-to-state stability (ISS) of fixed-point state-space digital filters in the presence of saturation overflow arithmetic and external interference. By utilizing an augmented Lyapunov function and the passivity property associated with multiple saturation nonlinearities, a new criterion for the ISS of interfered digital filters with saturation is proposed. When the external interference is present, the criterion can be used to determine ISS of digital filters. Without the external interference, the criterion is capable of detecting the asymptotic stability of digital filters. The proposed ISS criterion is in linear matrix inequality framework and, hence, is computationally tractable. The obtained criterion turns out to be less conservative than a recently reported ISS criterion. The superiority of the presented approach over the existing techniques is confirmed by numerical examples.

New realizability criterion for digital filters with external disturbance and saturation arithmetic

An improved stability criterion for fixed-point state-space digital filters in the occurrence of external disturbance and saturation nonlinearities by using induced l∞ approach is presented. The realization of state-space digital filters which is free from limit-cycles is brought out by utilizing a better characterization of the saturation nonlinearities and free-weighting matrices. The proposed criterion promises exponential stability and also diminishes the influence of external disturbance to a prescribed induced l∞ norm constraint. The superiority of the suggested method for filter design is exemplified by means of numerical examples.

Design and Realization of FIR Digital Filter for Optical IM/DD-OFDM System Using FPGA

We present a finite impulse response (FIR) filter by using field programmable gate array (FPGA). It is designed in MATLAB, and we get filter coefficient from it. The implementation results showed decent performance in filtering.

Realization of a recursive digital filter based on penalized splines

In this paper the possibility of development of the recursive digital filter using a P-spline is considered. The frequency and time response of the spline filter for real-time data are analytically obtained and investigated. The influence of the P-spline parameters on effectiveness of interpretation is explored with input metrical data. The patterns obtained during spline filter frequency analysis are confirmed by an example of Doppler function restoration.

Implementation of fractional order filters discretized by modified Fractional Order Darwinian Particle Swarm Optimization

Digital systems are placed at the core of information technology and they are used extensively in electronics. The digital filter realization has become a central topic of signal processing studies. This paper presents a discrete IIR filter design method for approximate realization of fractional order continuous filters in digital systems. For this purpose, Fractional Order Darwinian Particle Swarm Optimization (FODPSO) method is modified to provide better fitting of a discrete IIR filter function to a fractional order continuous filter and we implemented a hybrid version of FODPSO method, where the initial particle generation is carried out by arithmetical candidate point selection technique of the Base Optimization Algorithm (BaOA). This modification expands the search range of the FODPSO and thus the optimized discrete IIR filter can provide better approximation to amplitude response of fractional order continuous filter functions. In the paper, several illustrative examples are presented to demonstrate the performance of proposed methods.

A new realization of wave digital filters using GIC and fractional bilinear transform

In this paper, a new class of second-order digital filters is developed by using the concept of wave characterization, fractional bilinear transform and generalized immittance converter (GIC). These second-order digital filter sections are used as building blocks in cascade synthesis. During the realization procedure, fractional bilinear transform is utilized for analog to digital conversion to get more competent digital filter sections. The noise performance of the proposed filter sections is compared with that of already known GIC second order digital filter sections. The proposed synthesis yields lowpass and highpass filters with ameliorated signal to noise ratio in comparison to that of the conventional GIC digital filters.

A novel channelized FB architecture with narrow transition bandwidth based on CEM FRM

The two key requirements of channelized filter bank in the design of a digital receiver are low computational complexity and reconfigurability. Modulated discrete Fourier transform (MDFT) filter bank permits sub-channel with linear phase characteristics and provides high degree of computational efficiency. However, with sub-channel exhibiting narrow transition bandwidth in MDFT filter bank, the length of the prototype filter becomes long prohibitively, which can reduce the computational efficiency. It is well known that the frequency response masking (FRM) provides an attractive technique for the realization of digital filters with very narrow transition bandwidth. In this paper, the FRM digital filter design technique and another important technique named complex-exponential modulation (CEM) are exploited and applied to the design of a novel cascaded channelized filter bank to realize selective sub-channel with very narrow transition bandwidth. A simulation is provided to illustrate the design of the proposed CEM filter bank. It is shown that the resulting filter bank entails less computational complexity substantially and reduces multiplier resource consumption comparing to the conventional MDFT filter bank.

Realization of Low Power FIR Digital Filter using Modified DA-based Architecture

Objectives: Finite Impulse Response (FIR) filters are widely used in image and signal processing applications and responsible for more total power dissipation. This research work presents modified Distributed Arithmetic (DA)-based approach for realization of low power FIR digital filter. Methods/Statistical Analysis: Power reduction in modified DA-based filter is achieved by turning off the MOS components whenever the input samples of circuit are zero. The proposed filter reduces power consumption by disabling adder operation when inputs are zero. In the conventional DSP applications, it is observed that the average of the zero input sample is very high. Therefore, substantial reduction in power consumption can be obtained by proposed modified DA-based architecture. The proposed DA-based FIR filter is designed using Xilinx® ISE design tool and Cadence® EDA tool. Findings: The proposed work proved that the power reduction is achieved in modified DA-based FIR filter realization when compared with existing LUT-less DA-based architecture of FIR filter. Simulation results shows that proposed architecture can achieve significant power reduction with fewer percentage increases in area and delay for different architectures. For four tap FIR filter 12.5% power reduction is achieved, at the cost of 0.63% extra chip area and 1% increased delay in comparison with conventional DA-based filter architecture. Therefore, the proposed filter can achieve even greater power saving for higher order FIR filters and for more number of zeros in the inputs sample. The proposed technique can also be used for reconfigurable architectures where filter coefficients change during runtime. Conclusion: A low power modified DA-based FIR digital Filter is proposed. Power reduction in proposed design is due to turning off MOS components and is linearly related to number of zeros in input and order of the filter.

Multiplierless Implementation of Digital Colored Noise Generator

Colored noise can be generated by filtering of the white noise. It is a simple task. However, it becomes challenging if high operating speed of the generator is required. The realization of digital filter generally requires one multiplication per coefficient. Therefore, a high operating speed is achieved only with the cost of several general-purpose multipliers. In this paper, a multiplierless realization of the colored noise generator is proposed. It is based on the filtering of 1-bit random signal by a finite impulse response filter. The design of the generator is described and its implementation is considered. Furthermore, an application is described in which the proposed generator is used in mitigation of undesired effects caused by nonlinearities in an analog to digital converter.

Two new criteria for the realization of interfered digital filters utilizing saturation overflow nonlinearity

In this paper, an input-to-state stability (ISS) approach is used to derive two new criteria for the realization of fixed-point state-space and direct-form digital filters with saturation overflow nonlinearity and external interference via augmented Lyapunov functions. The two proposed realization criteria ensure ISS for external interference. Moreover, these criteria guarantee asymptotic stability without external interference. They take the form of linear matrix inequality (LMI) and, hence, are computationally tractable. Illustrative examples demonstrate the effectiveness of the two proposed criteria.