Real-time Threads Research Articles

A simultaneous multithreading processor architecture with predictable timing behavior

Real-time embedded systems need software and hardware to be time-predictable to guarantee the correct behavior of the system. Precision Timed Machines are architectures designed for timing predictability and repeatability. They help to improve design time and the efficiency of real-time embedded systems by allowing to separately verify the timing properties of modules. This paper presents a Simultaneous Multithreading Precision Timed Machine named Hivek-RT that can execute hard real-time and conventional threads in parallel. It employs a repeatable thread-interleaved pipeline with an exposed memory hierarchy composed of scratchpads, caches, and a predictable SDRAM memory controller. The proposed architecture is well suited for real-time embedded systems as experimentation results show that the proposed architecture has improved throughput, presents low memory footprint and achieve a memory bandwidth of 90% of the theoretical value while providing deterministic time access to the memory hierarchy. This paper is an extended version of the paper presented on the 8th Brazilian Symposium on Computing Systems Engineering.

리눅스 사용자 영역에 실시간성 제공을 위한 미들웨어

리눅스는 범용 운영체제로 스케줄링 특성 상 실시간성을 제공할 수 없는 단점이 있으며, 이를 해결하기 위해 RTiK-Linux을 통해 커널 영역에 실시간성을 지원했다. 하지만 RTiK-Linux 개발 초기 단계로 사용자 영역을 지원하지 않아 실시간성을 요구하는 응용프로그램 개발에 어려움이 있다. 본 논문에서는 RTiK-Linux를 개선하여 사용자 영역에 실시간성을 제공하는 RTiK미들웨어를 설계 및 구현한다. RTiK 미들웨어는 응용 프로그램에서 프로세스 정보와 요청 주기 등록한 뒤, 시그널을 통해 요청한 주기에 따라 사용자 영역에 API를 통해 실시간성을 제공한다. 구현한 RTiK미들웨어의 성능 검증 및 평가를 위해 RDTSC 명령어를 사용하여 생성된 실시간 쓰레드의 주기를 측정하였고, 유저 영역의 1ms 주기에서 오차 범위 내에서 정상 동작함을 확인하였다. Linux it self does not support real-time. To solve this problem RTiK-Linux was designed to support real-time in the kernel space. However, since the user space does not support real-time, it is not easy to develop application. In this paper, we designed and implemented a RTiK-middleware to support real-time in the user space. RTiK-middleware provides real-time scheduling for user space through signal request period after to register process information with request period using apis on application. To evaluate the performance of the proposed RTiK-middleware, we measured the periods of generated real-time threads using RDTSC instructions, and verified that RTiK-middleware operates correctly within the error ranges of 1ms.

Configuration-defined control algorithms with the ASDEX Upgrade DCS

The ASDEX Upgrade Discharge Control System (DCS) is a distributed real-time control system executing complex control and monitoring tasks. Up to now, DCS control algorithms have been implemented by coding dedicated application processes with the C++ programming language. Algorithm changes required code modification, compilation and commissioning which only experienced programmers could perform. This was a significant constraint of flexibility for both control system operation and design.The new approach extends DCS with the capability of configuration-defined control algorithms. These are composed of chains of small, configurable standard function blocks providing general purpose functions like algebraic operations, filters, feedback controllers, output limiters and decision logic. In a later phase a graphical editor could help to compose and modify such configuration in a Simulink-like fashion.Building algorithms from standard functions can result in a high number of elements. In order to achieve a similar performance as with C++ coding, it is essential to avoid administrative bottlenecks by design. As a consequence, DCS executes a function block chain in the context of a single real-time thread of an application process. No concurrency issues as in a multi-threaded context need to be considered resulting in strongly simplified signal handling and zero performance overhead for inter-block communication. Instead of signal-driven synchronization, a block scheduler derives the execution sequence automatically from the block dependencies as defined in the configuration. All blocks and connecting signals are instantiated dynamically, based on definitions in a configuration file. Algorithms thus are not defined in the code but only in the configuration.The concept has been developed in view of Simulink block libraries and MARTe General Application Modules (GAM) but extends these with the DCS virtues of distributed computing and multi-threading.With growing diversity of general-purpose blocks the DCS framework will reach an unprecedented degree of universality and flexibility. Configuration-defined algorithms will gradually replace many existing DCS applications. Finally, the concept might also become of interest for the upcoming ITER plasma control system.

An optimized data integration model based on reverse cleaning for heterogeneous multi-media data

With the continuous development of information technology, various multi-media data are constantly emerging and presents the characteristics of autonomous and heterogeneous, how to integrate and analysis data more correctly and efficiently has become a challenging problem. Firstly, in order to improve the quality of the integrated data, two real-time threads combined with data adapter are used to monitor and refresh necessary updates from heterogeneous data efficiently. Once the original data has been updated, the real-time data will be loaded into the data center soon. Secondly, a data reverse cleaning method is proposed to improve the data quality. It uses the data source tree that built in the data integration process to find the location of the original data quickly after reverse cleaning. finally, a data accuracy assessment algorithm is designed for data quality assessment, which is based on Bayesian network and the path condition algorithm. Experimental results show that the quality of the integrated data significantly higher than the quality of the original data.

Hardware-software Complex Prototyping for the Pulse Power Supply Control System of Tokamak T-15

Abstract A new hardware-software complex for digital control of a pulse power supply system was de- veloped for the tokamak T-15 upgrade. Special controller software provides implementation of flexible digital control of semiconductor converters. For most functions it is required that the software should keep control loop timing accurately. The complex software runs under the Linux operating system. To turn it into a real-time system open-source Xenomai framework was used. To test the framework applicability for the tasks of power sources control a research of a test system executing the basic functions of a real system was conducted. The required cycle was accomplished by separation of important tasks into real-time threads while using previously developed program code and libraries, which were already tested in the real system for non-real-time task without significant changes.

Parallel Task Management Library for MARTe

The Multithreaded Application Real-Time executor (MARTe) is a real-time framework with increasing popularity and support in the thermonuclear fusion community. It allows modular code to run in a multi-threaded environment leveraging on the current multi-core processor (CPU) technology. One application that relies on the MARTe framework is the Joint European Torus (JET) tokamak WAll Load Limiter System (WALLS). It calculates and monitors the temperature on metal tiles and plasma facing components (PFCs) that can melt or flake if their temperature gets too high when exposed to power loads. One of the main time consuming tasks in WALLS is the calculation of thermal diffusion models in real-time. These models tend to be described by very large state-space models thus making them perfect candidates for parallelisation. MARTe’s traditional approach for task parallelisation is to split the problem into several Real-Time Threads, each responsible for a self-contained sequential execution of an input-to-output chain. This is usually possible, but it might not always be practical for algorithmic or technical reasons. Also, it might not be easily scalable with an increase in the number of available CPU cores. The WorkLibrary introduces a “GPU-like approach” of splitting work among the available cores of modern CPUs that is (i) straightforward to use in an application, (ii) scalable with the availability of cores and all of this (iii) without rewriting or recompiling the source code. The first part of this article explains the motivation behind the library, its architecture and implementation. The second part presents a real application for WALLS, a parallel version of a large state-space model describing the 2D thermal diffusion on a JET tile.

Scheduling and thread management with RTEMS

The goal of a real-time operating system (RTOS) is to support real-time and embedded system (RT/ES) application development, which differ from general-purpose applications because of the size, weight, and power (SWaP) and timing constraints imposed by embedded applications. Useful RTOS features include real-time thread scheduling, thread communication, synchronization, interrupt handling, memory management, file systems, device drivers, networking, and debugging support. The Real-Time Executive for Multi-processor Systems (RTEMS) is a free and open-source RTOS that supports over a dozen processor architecture families and over 150 embedded system boards. RTEMS is designed to support embedded applications with stringent real-time requirements while being compatible with open standards such as POSIX. RTEMS includes optional services such as TCP/IP networking and file systems while still offering minimum executable sizes under 20 KB in useful configurations. One of the primary functions of an RTOS is to select threads that can obtain access to resources such as shared memory and processor time. RTEMS uses multiple algorithms to manage both waiting threads and those ready to execute. The thread execution schedulers include the traditional RTOS round robin and deterministic priority schedulers, rate monotonic, earliest deadline first (EDF), constant bandwidth server (CBS), and simple SMP scheduling algorithms. The RTEMS scheduling framework allows the application developer to select the thread scheduling algorithm that best meets the application's space and time requirements. ÂăWe will present how this framework can be used by researchers to integrate their own scheduling algorithm into RTEMS and test it using a scheduling simulator before deploying it on target hardware.

태블릿 PC 환경의 실시간 처리 기능 지원

태블릿 PC의 경우 개발의 편의성 및 다양한 기능을 제공하기 위해 모바일 운영체제인 윈도우 8을 사용하는데 윈도우 계열의 경우 실시간 처리를 보장하지 못하는 문제점이 있다. 또한 기존의 상용 솔루션과 RTiK 계열의 경우 윈도우와는 독립적인 타이머 인터럽트를 생성하기 위해 사용했던 로컬 APIC 타이머 카운트 값을 얻어 올 수 없기 때문에 실시간 처리 기능을 제공하기 어려운 문제점이 있다. 따라서 본 논문에서는 태블릿 PC의 윈도우 8환경에 실시간 처리 기능을 제공하기 위해 MSR_FSB_FREQ 레지스터를 이용하여 로컬 APIC 초기 카운트 값을 설정하였다. 또한 윈도우의 저전력 기법인 C-State를 제어함으로써 생성한 타이머 인터럽트의 주기성을 보장하여 실시간 처리 기능을 제공하는 RTiK+를 설계 및 구현하였다. 구현한 RTiK+의 성능 검증 및 평가를 위해 CPU 클럭 틱의 수를 반환하는 RDTSC 명령어를 사용하여 생성된 실시간 쓰레드의 주기를 측정하였고, 1ms 주기에서 오차범위 내에서 정상 동작함을 확인하였다. Generally in case of tablet PC's, the Windows 8 is used to support various functions or development convenience, however it cannot support real-time processing. In addition, existing commercial solutions and RTiK has a problem to support real-time processing due to impossibility of getting APIC timer count value which is used to generate timer interrupt separated from that of Windows. Thus, in this paper, we set the initial APIC count value using MSR_FSB_FREQ to support real-time processing on the Windows 8-based tablet PC's. Additionally, we deal with designing and implementing RTiK+ providing real-time processing to guarantee interrupt periods by controlling C-State which is used for low power techniques. To evaluate the performance of the proposed RTiK+, we measured the periods of generated real-time threads using RDTSC instructions which return the number of CPU clock ticks, and verified that RTiK+ operates correctly within the error ranges of 1ms.

Low-cost and power-efficient thread collision detection scheme for shared caches in a real-time multithreaded embedded processor

This paper addresses an important issue in a real-time multithreaded embedded processor where several active hardware threads share the critical resources such as caches in the processor. Thread interferences or collisions could lead to severe performance degradations on the real-time threads. Although the cache interference issue on real-time multithreaded processors has been studied before, no cost-effective and simpler hardware solutions were proposed to maintain the single thread performance of the real-time thread while still letting the low-priority threads progress. A novel technique called collision tag is proposed to address these issues. Progressively, the collision tag scheme can be reduced into a more power-efficient form called collision bit vector, with almost no impact in the overall performance of the real-time multithreaded embedded processor.

Static Timing Analysis of Shared Caches for Multicore Processors

The state-of-the-art techniques in multicore timing analysis are limited to analyze multicores with shared instruction caches only. This paper proposes a uniform framework to analyze the worst-case performance for both shared instruction caches and data caches in a multicore platform. Our approach is based on a new concept called address flow graph, which can be used to model both instruction and data accesses for timing analysis. Our experiments, as a proof-of-concept study, indicate that the proposed approach can accurately compute the worst-case performance for real-time threads running on a dual-core processor with a shared L2 cache (either to store instructions or data).

Real-time Java in modernization of the aegis weapon system

The U.S. Navy's Aegis system, considered to be the "shield of the fleet", provides area air defense for a carrier battle group in addition to providing long-range ballistic missile defense. A typical Aegis deployment consists of about 100 computers, many of which have multiple cores. The application is distributed, with typical real-time threads spanning 4 or 5 different computers. End-to-end distributed thread timing constraints measured from stimulus to response are typically under 100 ms. The target jitter constraints on the individual contributions of processors to the end-to-end deadline constraint are well below 1 ms. The system is fully redundant to support fault tolerance. The software is considered to be safety critical because it aims and fires weapons. The Aegis Weapons System software was recently rewritten into real-time Java as part of the Aegis Modernization activity. This project involved replacement of about 200,000 lines of CMS-2 and Ada code with roughly 500,000 lines of Java. The effort began in 2003 and the new Java implementation of Aegis Weapons System is now being deployed on warships. This paper describes the motivation for the modernization effort and provides a summary of Lockheed Martin's experiences with this project.

A Model Checking Based Approach to Bounding Worst-Case Execution Time for Multicore Processors

As multicore processors are increasingly adopted in industry, it has become a great challenge to accurately bound the worst-case execution time (WCET) for real-time systems running on multicore chips. This is particularly true because of the inter-thread interferences in accessing shared resources on multicores, such as shared L2 caches, which can significantly affect the performance but are very difficult to be estimated statically. This article proposes an approach to analyzing WCET for multicore processors with shared L2 instruction caches by using a model checking based method. We model each concurrent real-time thread, including the inter-thread cache interferences with a PROMELA process, and derive the WCET by using a binary search algorithm. To reduce the state explosion problem, we propose several techniques for reducing the memory consumption by exploiting domain-specific information. Our experiments indicate that compared to the static analysis technique based on extended ILP (integer linear programming), our approach improves the tightness of WCET estimation by more than 31.1% for the benchmarks we studied. However, due to the inherent complexity of multicore timing analysis and the state explosion problem, the model checking based approach currently can only work with small real-time kernels for dual-core processors.

Multicore-Aware Code Co-Positioning to Reduce WCET on Dual-Core Processors with Shared Instruction Caches

For real-time systems it is important to obtain the accurate worst-case execution time (WCET). Furthermore, how to improve the WCET of applications that run on multicore processors is both significant and challenging as the WCET can be largely affected by the possible inter-core interferences in shared resources such as the shared L2 cache. In order to solve this problem, we propose an innovative approach that adopts a code positioning method to reduce the inter-core L2 cache interferences between the different real-time threads that adaptively run in a multi-core processor by using different strategies. The worst-case-oriented strategy is designed to decrease the worst-case WCET among these threads to as low as possible. The other two strategies aim at reducing the WCET of each thread to almost equal percentage or amount. Our experiments indicate that the proposed multicore-aware code positioning approaches, not only improve the worstcase performance of the real-time threads but also make good tradeoffs between efficiency and fairness for threads that run on multicore platforms.

Multiprocessors and Asynchronous Event Handling in the Real-Time Specification for Java

The Real-Time Specification for Java (RTSJ) is silent on multiprocessor issues. It attempts not to preclude multiprocessor implementations but provides no direct support. Many areas of the RTSJ leave an implementation considerable freedom on how it provides the defined functionality. One such area is the asynchronous event handling (AEH) model. Events are fired and associated handlers are scheduled for execution in response; handlers have defined scheduling parameters and deadlines. The primary goal of the AEH model is to support a lightweight real-time concurrency model. Hence handlers, in general, do not have dedicated threads. Rather, the implementation is responsible for ensuring that all handlers meet their deadlines. Typically real-time threads are assigned to execute handlers by the implementation. This paper discusses the issues associated with implementing the AEH model on multiprocessor systems. The emphasis here is on achieving a lightweight model. A model is lightweight if it is able to meet the deadlines of all handlers with as few as possible real-time threads. In the RTSJ this is made more complicated because asynchronous event handlers are allowed to suspend themselves (for example, by waiting on a monitor condition). Such handlers are called blocking handlers. Most of an implementation's freedom comes from being able to optimize the support for those handlers that do not block. The paper first examines all possible releasing sequences of non-blocking handlers on multiprocessor systems. Based on this, it proposes an efficient and scalable AEH mapping model for multiprocessor systems, which limits the number of real-time threads even in the worst case while retaining the schedulability of the system. The proposed model is then examined to prove its safety and liveness requirements using a model checking tool, UPPAAL. The verification and simulation results of the model indicate that the safety and liveness requirements are satisfied. Most importantly, this paper derives the proposed model's greatest lower and least upper bounds of real-time threads required to execute a given number of non-blocking handlers. The greatest lower bound is equal to the number of processors, and the least upper bound is equal to the number of processors times that of the priority levels in the system. In the model, the number of real-time threads required to execute a given number of non-blocking handlers is restricted to between these two bounds depending on the releasing sequence of handlers. Even in the worst case, the model requires the least upper bound of real-time threads which is, in most cases, considerably less than the actual number of handlers in the system. This, in turn, enables the proposed model to be efficient and scalable by reducing time and space overheads, compared with a traditional 1:1 AEH mapping model where each handler is mapped to a single thread.

Using Sun’s Java Real-Time System to Manage Behavior-Based Mobile Robot Controllers

Implementing a robot controller that can effectively manage limited resources in a deterministic, real-time manner is challenging. Behavior-based architectures that decompose autonomy into levels of intelligence are popular due to their robustness but do not provide real-time features that enforce timing constraints or support determinism. We propose an architecture and approach for using the real-time features of the Real-Time Specification for Java (RTSJ) in a behavior-based mobile robot controller to show that timing constraints affect performance. This is accomplished by extending a real-time aware architecture that explicitly enumerates timing requirements for each behavior. It is not enough to reduce latency. The usefulness of this approach is demonstrated via an implementation on Solaris 10 and the Sun Java Real-Time System (Java RTS). Experimental results are obtained using a K-team Koala robot performing path following with four composite behaviors. Experiments were conducted using several task period sets in three cases: real-time threads with the real-time garbage collector, real-time threads with the non- real-time garbage collector, and non-real-time threads with the non-real-time garbage collector. Results show that even if latency and determinism are improved, the timing of each individual behavior significantly affects task performance.

Efficient asynchronous event handling in the real-time specification for Java

The Real-Time Specification for Java (RTSJ) is becoming mature. It has been implemented, formed the basis for research and used in serious applications. Some strengths and weaknesses are emerging. One of the areas that requires further elaboration is asynchronous event handling (AEH). The primary goal for handlers in the RTSJ is to have a lightweight concurrency mechanism. Some implementation will, however, simply map a handler to a real-time thread and this results in undermining the original motivations and introduces performance penalties. However it is generally unclear how to map handlers to real-time threads effectively. Also the support for nonblocking handlers in the RTSJ is criticized as lacking in configurability as implementations are unable to take advantage of them. This article, therefore, examines the AEH techniques used in some popular RTSJ implementations and proposes two efficient AEH models for the RTSJ. We then define formal models of the RTSJ AEH implementations using the automata formalism provided by the UPPAAL model checking tool. Using the automata models, their properties are explored and verified. In the proposed models, blocking and nonblocking handlers are serviced by different algorithms. In this way, it is possible to assign a real-time thread to a handler at the right time in the right place while maintaining the fewest possible threads overall and to give a certain level of configurability to AEH. We also have implemented the proposed models on an existing RTSJ implementation, jRate and executed a set of performance tests that measure their respective dispatch and multiple-handler completion latencies. The results from the tests and the verifications indicate that the proposed models require fewer threads on average with better performance than other approaches.

Scheduling of hard real-time garbage collection

Automatic memory management or garbage collection greatly simplifies development of large systems. However, garbage collection is usually not used in real-time systems due to the unpredictable temporal behavior of current implementations of a garbage collector. In this paper we propose a real-time garbage collector that can be scheduled like a normal real-time thread with a deadline monotonic assigned priority. We provide an upper bound for the collector period so that the application threads will never run out of memory. Furthermore, we show that the restricted execution model of the Safety Critical Java standard simplifies root scanning and reduces copying of static data. Our proposal has been implemented and evaluated in the context of the Java processor JOP.

Architecture d'un processeur multiflot orienté temps-réel

Simultaneous multithreading (SMT) processors might be good candidates to fulfill the ever increasing performance needs of embedded applications. However, off-the-shelves SMT architectures do not fit the timing predictability requirements of hard real-time systems: to schedule critical threads so that they are guaranteed to meet their deadlines, it is necessary to estimate their Worst-Case Execution Times which is not possible when simultaneous threads might interfere. In this paper, we propose an SMT architecture designed to enforce isolation of hard real-time threads so that their worst-case execution time can be safely estimated. We report experimental results that show that this architecture still provides a high level of performance and we give an insight into how the thread isolation feature could be controlled by a real-time task scheduler.

It's Time for a Change: The Sun Java Real-Time System for Automation Systems

The Sun Java Real-Time System (Java RTS) 2.0 was released as a produce in June of 2007. This release includes several innovative features new to Sun and Java; real-time garbage collection and initialization-time compilation. Additionally, this release offers customers remarkable precision in the control of the execution of logic in the temporal dimension.The Java Platform requires, for any usable implementation, internal processes which automatically collect and return to the free pool unused blocks of memory. Typically called garbage collection this internal process executes in, what is essentially, opposition to the application in its access to the memory referencing data word topology (reference topology from now on) and in its movement and access to application defined blocks of memory (objects from now on). Garbage collectors need, at some level, to synchronize with the application to avoid mutually destructive simultaneous access to the reference topology and objects. Two points we can now assert, garbage collectors require processor cycles, i.e., overhead, to complete their work and garbage collectors contend with the application for access to application data structures; hence garbage collectors introduce inconsistencies in the execution of logic when viewed in the temporal dimension. For general-purpose applications these inconsistencies, also known as pause times, are currently small enough to be unnoticeable in all but the most demanding applications. For applications which control and monitor physical machines or processes, e.g., robots, cars, trains, oil refineries, manufacturing systems, financial markets, etc., these pause times are too large by three orders of magnitude and in the past have completely eliminated the possibility of using the Java Platform to develop and execute such applications.Java Specification Request 01, finalized in 2001, known as The Real-Time Specification for Java (RTSJ), defines libraries and semantics which when implemented in a Java Virtual Machine (JVM) give developers and, consequently, applications precise control over temporal behavior. The semantics are a strict subset of the semantics of the general-purpose Java Platform which means that implementation of JSR-01 or the RTSJ are, in fact, also conforming implementations of the general-purpose Java Platform. The RTSJ offers developers a rich and deep set of abstractions in which logic can be executed but the one we are interested in is instances of RealtimeThread (RTT), (a class in the RTSJ which is a subclass of Thread). In all observable dimensions and function except the temporal domain logic executing in the context of an RTT is exactly equivalent to that logic executing in the context of a Thread.

A software oriented CNC system based on Linux/RTLinux

The software-oriented CNC is one of the ideal solutions for open architecture CNC. However, its implementation is a difficult task, especially the guarantee of system’s real-time performance. In this paper, a software oriented CNC system named Lin-soft CNC, whose operating system (OS) is Linux with its real-time extension - RTLinux - was proposed and depicted. The proposed system consists of four layers: the GUI, non-real-time layer, real-time layer and driver layer. Both the system and subsystem layout are detailed, along with the relevant implementation detail, such as the hierarchy design and the data communication between layers. Furthermore, the real-time layer has been identified as the kernel of the system, in which a simple and effective strategy - rational design of data buffer and high precision period of the real-time thread - is adopted to guarantee the real-time performance. At last, the prototype controller and test results are present.