Real-time Digital Signal Processing Applications Research Articles

Configurable Folded IIR Filter Design

This brief proposes an efficient very-large-scale integration architecture for folded configurable infinite-impulse response (IIR) filter design, which is used in modern real-time digital signal processing applications such as loudspeaker equalization. The proposed configurable sixth-order IIR filter is designed with three cascaded second-order IIR filters, and the same is used to perform one sixth-order or three second-order or one fourth-order and one second-order IIR filter operations in parallel, where floating-point multiply–accumulate circuit (MAC) is used to design each second-order IIR filter. The proposed sixth-order IIR filter achieves a 58.4% reduction in energy per operation compared with conventional MAC-based architecture using 45-nm technology.

Hands-On DSP Education through Experiments

A new graduate from electrical engineering education must know about digital signal processing (DSP) to find a secure place in the competitive jobs market. Although this topic can be taught theoretically, its importance comes from practical applications. Therefore, students must be equipped with appropriate tools. Fortunately, DSP platforms serve this purpose. At Yeditepe University, we established a laboratory to guide students in real-time digital signal processing applications. We selected a Texas Instruments TMS320C6713 DSK platform for this purpose. In this study, we provide several laboratory applications on this platform. We also provide more advanced projects developed by our students which emerged from these applications. We observed that this laboratory improved the understanding of theoretical DSP concepts.

Remotely Controlled Real-Time DSP Applications through Customized GUIs based on LabVIEW

The purpose of this paper is to present an approach which could expand the features of Remote Laboratories focused on embedded Digital Signal Processing (DSP) systems. The proposed approach is based on a system which is designed and developed with LabVIEW and is called R-DSP Server. Exploiting this system, users are able to develop their own Graphical User Interfaces (GUIs), named Customized GUIs, for the remote control and validation of real-time DSP applications. These GUIs are tailored to the needs of each DSP application and can be implemented in any programming language. The rapid design of Customized GUIs using LabVIEW for the communication with the R-DSP Server is achieved utilizing an implemented set of functions, called R-DSP LabVIEW Toolkit.

FPGA-based digit-serial CSD FIR filter for image signal format conversion

This paper proposes the FPGA implementation of the digit-serial Canonical Signed-Digit (CSD) coefficient FIR filters which can be used as format conversion filters in place of the ones employed for the MPEG2 TM 5 (test model 5). Canonical representation of a signed digit (CSD) is a method used to reduce cost by representing a signed number using the least amount of non-zero digits, thereby reducing the number of multiply operations. As Field Programmable Gate Arrays (FPGAs) have grown in capacity, improved in performance, and decreased in cost, they are becoming a viable solution for performing computationally intensive tasks, with the ability to tackle applications formerly reserved for custom chips and programmable digital signal processing (DSP) devices. A digit-serial CSD FIR filter design is realized and practical design guidelines are provided using FPGAs. An analysis of the performance comparison of bit-serial, serial distributed arithmetic, and digit-serial CSD FIR filters on a Xilinx XC4000XL-series FPGA is described. The results show that the proposed digit-serial CSD FIR filter is compact and an efficient implementation of real-time DSP applications on FPGAs.

A fast task-to-processor assignment heuristic for real-time multiprocessor DSP applications

The optimal assignment of the tasks to the processors to minimize total delay in a multiprocessor digital signal processing (DSP) architecture is extremely difficult, particularly for systems of many (e.g. 100) tasks. Two factors especially complicate the problem: (1) the multiprocessor architecture affects the inter-processor communication times, and (2) the specific assignment of tasks to processors affects the inter-task communication times. We develop a fast heuristic for assigning tasks to processors. There are two main ingredients in our method: (i) the choice of a useful general-purpose multiprocessor architecture for DSP applications, and (ii) an adaptive list-ordering heuristic which takes advantage of knowledge of the inter-processor communication characteristics of the chosen architecture. Examples are given, including comparisons to exact branch-and-bound methods, and a large sonar example. Scope and purpose General digital signal processing system architectures consist of an arrangement of signal processing units connected by communication links. The tasks to be carried out by the signal processing units are specified via a task graph similar to a PERT diagram. The challenge is to assign the tasks in the task graph to the signal processing units in the architecture in an optimal manner. In this paper, we are interested in task-to-processor assignments that minimize the total delay, which is the lag between the first appearance of a signal at the input port and the production of a processed signal at the output port. The assignment process is complicated by the need to consider the inter-task communication delays, which are themselves greatly affected by the assignment. The task-to-processor assignment problem is NP-complete, hence heuristics must be used. We develop a fast and effective heuristic for a specific general-purpose digital signal processing architecture.

An innovative course emphasizing real-time digital signal processing applications

This paper presents an innovative undergraduate real-time digital signal processing (DSP) course, Digital Signal Processors, which emphases hands-on experiments and practical applications. It enables students to experiment with sophisticated DSP applications to augment the theoretical, conceptual, and analytical material provided in their first DSP course, Digital Filter Design. The inclusion of both software and hardware developmental experiences permits undergraduates to undertake a wide range of real-time DSP projects in their required Senior Engineering Design course. This paper briefly introduces representative examples of some challenging DSP applications, such as acoustic echo cancellation, active noise control, and image compression.

A reconfigurable multiprocessor IC for rapid prototyping of algorithmic-specific high-speed DSP data paths

A field-programmable multiprocessor integrated circuit, PADDI (programmable arithmetic devices for high-speed digital signal processing), has been designed for the rapid prototyping of high-speed data paths typical to real-time digital signal processing applications. The processor architecture addresses the key requirements of these data paths: (a) fast, concurrently operating, multiple arithmetic units, (b) conflict-free data routing, (c) moderate hardware multiplexing (of the arithmetic units), (d) minimal branch penalty between loop iterations, (e) wide instruction bandwidth, and (f) wide I/O bandwidth. The initial version contains eight processors connected via a dynamically controlled crossbar switch, and has a die size of 8.9*9.5 mm in a 1.2- mu m CMOS technology. With a maximum clock rate of 25 MHz, it can support a computation rate of 200 MIPS and can sustain a data I/O bandwidth of 400 Mbytes/s with a typical power consumption of 0.45 W. An assembler and simulator have been developed to facilitate programming and testing of the chip.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Advance Announcement... Tutorial Week 80

Modification of the original algorithm by Allum1yields a computationally efficient algorithm. The computational improvement, nominally 20 percent, is significant when real-time digital signal processing applications are involved.

Modification of "A Least Mean Squares Cubic Algorithm for On-Line Differential of Sampled Analog Signals"

Modification of the original algorithm by Allum1yields a computationally efficient algorithm. The computational improvement, nominally 20 percent, is significant when real-time digital signal processing applications are involved.