Real-time Codec Research Articles

Development of 4K/8K Real-time Codec Compliant with H.266 | VVC

Development of 4K/8K Real-time Codec Compliant with H.266 | VVC

A Low Power Shift Add Multiplier for Lifting Based Dwt using Kogge Stone Adder

The most common technique used for image processing applications is ‘The wavelet transformation’. The Discrete Wavelet Transform (DWT) keeps the time as well as frequency information depend on a multi resolution analysis structure, where the other classical transforms like Fast Fourier Transform (FFT), Discrete Cosine Transform (DCT) will not do that. Because of this feature, the quality of the repaired image is improved when comparing to the other transforms. To implement the DWT on a real time codec, a fast device needs to be targeted. While comparing with the other implementation such as PCs, ARM processors, DSPs etc, Field Programmable Gate Array (FPGA) implementation of DWT had better processing speed and costs were vey less. A Fast Architecture based DWT using Kogge Stone Adder is proposed in this paper where the coefficients of lifting scheme are calculated by using Shift adder and Kogge Stone Adder where other techniques used multiplier. The most important intention of the suggested technique is to use minimum calculation and limited memory. The simulation of the suggested design is dole out on the Xilinx 14.1 style tool and also the performance is evaluated and compared with the present architectures.

A Low Power Shift Add Multiplier for Lifting Based Dwt using Kogge Stone Adder

The most common technique used for image processing applications is ‘The wavelet transformation’. The Discrete Wavelet Transform (DWT) keeps the time as well as frequency information depend on a multi resolution analysis structure, where the other classical transforms like Fast Fourier Transform (FFT), Discrete Cosine Transform (DCT) will not do that. Because of this feature, the quality of the repaired image is improved when comparing to the other transforms. To implement the DWT on a real time codec, a fast device needs to be targeted. While comparing with the other implementation such as PCs, ARM processors, DSPs etc, Field Programmable Gate Array (FPGA) implementation of DWT had better processing speed and costs were vey less. A Fast Architecture based DWT using Kogge Stone Adder is proposed in this paper where the coefficients of lifting scheme are calculated by using Shift adder and Kogge Stone Adder where other techniques used multiplier. The most important intention of the suggested technique is to use minimum calculation and limited memory. The simulation of the suggested design is dole out on the Xilinx 14.1 style tool and also the performance is evaluated and compared with the present architectures.

Design of a low-power real-time wavelet CODEC circuit

Abstract This paper presents the architecture and design of a CODEC circuit that can compress and reconstruct 4:2:2 color VGA video images using two-dimensional DWT. For real-time operation and low-power consumption, we modified the traditional Mallat's sub-band coding method to reduce the amount of computation required in two-dimensional DWT. Using the modified method, two-dimensional DWT can be performed by two sets of one-dimensional DWT operations regardless of the number of decomposition levels. We adopted the systolic array architecture to design the circuit implementing our method. Our low-power real-time CODEC circuit was designed using Verilog HDL and fabricated as a VLSI chip using 0.35 μm 3.3 V CMOS standard cell process. We made a simple DVR system using our CODEC chip to store and retrieve the video image data to and from the hard disk, and observed successful real-time operations.

On fast firmware/software-based video coding

Video coding via firmware or software has the advantages of greater flexibility, quicker development cycle and easier updating/reconfiguration; in addition, its efficient and economical realization can be exploited at algorithm and programming/process levels. Issues related to complexity regulation and firmware/software efficiency are discussed for a hybrid video codec. A simple yet effective parametric scheme is proposed for high-level complexity regulation, regardless of the motion estimation (ME) and DCT algorithms adopted. Various methods are also presented for programming and process optimization. Results and performance in real-time codecs confirm the effectiveness of the techniques being presented.

A reservation principle with applications to the ATM traffic control

Abstract In a network based upon the Asynchronous Transfer Model (ATM), stepwise variable bit rate traffic sources can be efficiently multiplexed without significant degradation of the transfer equality by introducing an access control at an intermediate burst (step) level. This multiplexing is based upon a peak bit rate reservation in the switching elements of the general network. Two Fast Reservation Protocols (FRPs) are presented based upon mono-cell bandwidth management messages processed “on the fly” in the switching elements. The first protocol is FRP/DT which could be run to multiplex file banking calls and LAN-to-LAN interconnections using leased lines. The second is FRP/IT and could be run to multiplex connectionless servers and some real-time codecs. Evaluation of the hardware complexity and performance are addressed.