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A computational study of AlScN-based ferroelectric tunnel junction

Ferroelectric (FE) AlScN materials have been experimentally explored for memory and neuromorphic computing device applications. Here a computational study is performed to simulate the device characteristics and assess the performance potential of a ferroelectric tunnel junction (FTJ) based on AlScN. We parameterize an efficient k⋅p Hamiltonian from the complex band structure of AlScN from ab initio density-functional theory calculations to enable efficient quantum transport simulations of the FTJ device. Using a metal–FE–graphene structure enhances the barrier height modulation and the tunneling electroresistance (TER) ratio, compared to a metal–FE–semiconductor FTJ device structure. The barrier height modulation between ON and OFF states can reach ∼ 0.7eV with a FE polarization of 25 μC/cm2. Reducing the AlScN tunnel layer thickness is important for increasing the device ON current and reducing the read latency. The results indicate the importance of contact designs and FE layer thickness in the design of AlScN-based FTJ devices, and highlight the potential of AlScN FTJ for future memory device technology applications.

Ge n-Channel Hybrid Memory Based on Ferroelectric Charge Trapping Layer With Low Operating Voltage, Large Memory Window, and Negligible Read Latency

Ge n-Channel Hybrid Memory Based on Ferroelectric Charge Trapping Layer With Low Operating Voltage, Large Memory Window, and Negligible Read Latency

ReadGuard: Integrated SSD Management for Priority-Aware Read Performance Differentiation

When multiple apps with different I/O priorities share a high-performance SSD, it is important to differentiate the I/O QoS level based on the I/O priority of each app. In this paper, we study how a modern flash-based SSD should be designed to support priority-aware read performance differentiation. From an in-depth evaluation study using 3D TLC SSDs, we observed that existing FTLs have several weaknesses that need to be improved for better read performance differentiation. In order to overcome the existing FTL weaknesses, we propose ReadGuard , a novel priority-aware SSD management technique that enables an FTL to manage its blocks in a fully read-latency-aware fashion. ReadGuard leverages a new read-latency-centric block quality marker that can accurately distinguish the read latency of a block and ensures that higher-quality blocks are used for higher-priority apps. ReadGuard extends an existing suspend/resume technique to handle collisions among reads. Our experimental results show that a ReadGuard -enabled SSD is effective in supporting differentiated read performance in modern 3D flash SSDs.

A read-efficient and write-optimized hash table for Intel Optane DC Persistent Memory

Emerging non-volatile memory technologies are driving the next generation of storage systems and durable data structures. Among them, many hash table proposals employ NVM as the storage layer for both fast access and efficient persistence. Most of them are based on the assumption that NVM has cacheline access granularity, poor write endurance, DRAM-comparable read latency and relatively higher write latency. However, a commercial non-volatile memory product, namely Intel Optane DC Persistent Memory (Optane), has some interesting features that are different from previous assumptions, such as 256-byte OptaneLine access granularity, higher read latency than DRAM and DRAM-comparable write latency, limited read/write bandwidth, and hardware-layer wear-leveling. Confronted with the new challenges brought by Optane, we propose Rewo-Hash, a novel read-efficient and write-optimized persistent hash table. Our incremental contributions over our previous work are summarized as follows. First, provide a more detailed technical description for cached table-inclined read mechanism and log-free atomic write mechanism. Second, we devise a consistent shadowing synchronization scheme to mask the data synchronization overhead. Third, we propose a non-blocking lightweight resizing scheme and elaborate the crash recovery mechanism. Fourth, we conduct a comprehensive analysis of the implications of Intel ceasing the production of Optane, and provide a forward-looking perspective on the future of non-volatile memory. The experimental results show that compared with state-of-the-art NVM-Optimized hash tables, Rewo-Hash gains remarkable performance improvement.

DMMC: A Polar Code Construction Method for Improving Performance in TLC NAND Flash

3D TLC NAND flash memory significantly increases the storage capacity but makes data more prone to errors. To address the reliability problem, Polar Code is one coding method that can reach the channel capacity1. However, the 3D NAND flash memory channel is uncertain due to the variation of retention time and program/erase(P/E) cycle. So it is difficult to construct Polar Code in NAND flash memory. This paper proposes a new Polar Code construction method called Dynamic Merge Monte Carlo(DMMC). DMMC uses the Monte Carlo method to obtain the optimal Polar Code construction and then reduces the space overhead by combining similar construction so that it can be used in flash memory systems. Compared with the conventional method, the uncorrectable bit error rate(UBER) of the proposed method can reduce by up to 90.5%, and the read latency can reduce by more than 50%.

Overt Word Reading and Visual Object Naming in Adults with Dyslexia: Electroencephalography Study in Transparent Orthography.

The study aimed to investigate overt reading and naming processes in adult people with dyslexia (PDs) in shallow (transparent) language orthography. The results of adult PDs are compared with adult healthy controls HCs. Comparisons are made in three phases: pre-lexical (150-260 ms), lexical (280-700 ms), and post-lexical stage of processing (750-1000 ms) time window. Twelve PDs and HCs performed overt reading and naming tasks under EEG recording. The word reading and naming task consisted of sparse neighborhoods with closed phonemic onset (words/objects sharing the same onset). For the analysis of the mean ERP amplitude for pre-lexical, lexical, and post-lexical time window, a mixed design ANOVA was performed with the right (F4, FC2, FC6, C4, T8, CP2, CP6, P4) and left (F3, FC5, FC1, T7, C3, CP5, CP1, P7, P3) electrode sites, within-subject factors and group (PD vs. HC) as between-subject factor. Behavioral response latency results revealed significantly prolonged reading latency between HCs and PDs, while no difference was detected in naming response latency. ERP differences were found between PDs and HCs in the right hemisphere's pre-lexical time window (160-200 ms) for word reading aloud. For visual object naming aloud, ERP differences were found between PDs and HCs in the right hemisphere's post-lexical time window (900-1000 ms). The present study demonstrated different distributions of the electric field at the scalp in specific time windows between two groups in the right hemisphere in both word reading and visual object naming aloud, suggesting alternative processing strategies in adult PDs. These results indirectly support the view that adult PDs in shallow language orthography probably rely on the grapho-phonological route during overt word reading and have difficulties with phoneme and word retrieval during overt visual object naming in adulthood.

Compensation architecture design utilizing residual resource to mitigate impacts of nonidealities in RRAM-based computing-in-memory chips

Resistive random access memory (RRAM) is a promising technology for energy-efficient in-memory computing. However, due to technology limits, RRAM device faces a series of reliability issues. Deep neural network (DNN) computing based on RRAM suffers from accuracy degradation. On the one hand, offline DNN training solutions are difficult to fully consider and simulate all nonidealities. Worse still, new error or nonideality may come up with the usage of RRAM, which further deteriorates the effectiveness of offline training. On the other hand, online training poses great challenges on programming overhead and device lifetime. The iterative write-verify technique to program multi-bit RRAM cells prolongs write latency more than 10× longer than read latency. To overcome these issues, we propose a compensation architecture and training designs to mitigate the realistic accuracy loss in RRAM chips with negligible hardware resource for RRAM-based DNN computing. Firstly, we add trainable compensation channels in crossbars utilizing the residual resource after original weight mapping. Secondly, an offline training procedure with computing output from hardware is triggered to settle down appropriate weight value in compensation channels. Experimental results demonstrate that the proposed design can guarantee ≤ 0.8% loss of accuracy in DNN even when nonidealities reduce the original accuracy down to ≤73%.

Modeling Retention Errors of 3D NAND Flash for Optimizing Data Placement

Considering 3D NAND flash has a new property of process variation (PV) , which causes different raw bit error rates (RBER) among different layers of the flash block. This paper builds a mathematical model for estimating the retention errors of flash cells, by considering the factor of layer-to-layer PV in 3D NAND flash memory, as well as the factors of program/erase (P/E) cycle and retention time of data. Then, it proposes classifying the layers of flash block in 3D NAND flash memory into profitable and unprofitable categories, according to the error correction overhead. After understanding the retention error variation of different layers in 3D NAND flash, we design a mechanism of data placement, which maps the write data onto a suitable layer of flash block, according to the data hotness and the error correction overhead of layers, to boost read performance of 3D NAND flash. The experimental results demonstrate that our proposed retention error estimation model can yield a R 2 value of 0.966 on average, verifying the accuracy of the model. Based on the estimated retention error rates of layers, the proposed data placement mechanism can noticeably reduce the read latency by 29.8 % on average, compared with state-of-the-art methods against retention errors for 3D NAND flash memory.

A Contract-aware and Cost-effective LSM Store for Cloud Storage with Low Latency Spikes

Cloud storage is gaining popularity because features such as pay-as-you-go significantly reduce storage costs. However, the community has not sufficiently explored its contract model and latency characteristics. As LSM-Tree-based key-value stores (LSM stores) become the building block for numerous cloud applications, how cloud storage would impact the performance of key-value accesses is vital. This study reveals the significant latency variances of Amazon Elastic Block Store (EBS) under various I/O pressures, which challenges LSM store read performance on cloud storage. To reduce the corresponding tail latency, we propose Calcspar, a contract-aware LSM store for cloud storage, which efficiently addresses the challenges by regulating the rate of I/O requests to cloud storage and absorbing surplus I/O requests with the data cache. We specifically developed a fluctuation-aware cache to lower the high latency brought on by workload fluctuations. Additionally, we build a congestion-aware IOPS allocator to reduce the impact of LSM store internal operations on read latency. We evaluated Calcspar on EBS with different real-world workloads and compared it to the cutting-edge LSM stores. The results show that Calcspar can significantly reduce tail latency while maintaining regular read and write performance, keeping the 99 th percentile latency under 550μs and reducing average latency by 66%. In addition, Calcspar has lower write prices and average latency compared to Cloud NoSQL services offered by cloud vendors.

A Full Replicas-Based Data Store Scheme Inspired by Targeted Immunization of the Epidemic Theory in Smart Manufacturing

Cloud data centers (CDCs) have been used as the basic platforms for data storage in industrial scenarios such as smart manufacturing. However, a lack of effective data storage schemes exacerbates reading latency and replicas' inconsistency in the machine tools of smart facto- ries. In this study, we propose a full-replicas scheme (FRS) to attain the low latency reading and high data consistency required in smart manufacturing. First, inspired by the susceptible-infectious-recovered (SIR) epidemic model, the network bandwidth usage generated by FRS is adjusted by the targeted immunization principle. Then, the final break- out rate is derived as a function of the immunization rate, which can reduce the complexity of target immunization implementation in scale-free networks. Finally, the experi- mental results confirm our theoretical analysis and show that the FRS provides strong consistency with lower client- side reading latency.

The Performance of SRAM Cell Topologies with 6 T, 7 T, 8 TAnd 9 T Technologies at 45 Nm Technology node

Numerous SRAM cell architectures employing 45nm technology were simulated in the Tanner tool used for this inquiry. In every arrangement, variables like read latency, write delay, power read, power write consumption, read static noise margin (RSNM), and write static noise margin (WSNM) were examined. Of all the designs, the 7T SRAM cell stands out for having the lowest power read utilization. Nevertheless, compared to the 6T SRAM cell, the 8T SRAM cell displayed a 44.15% reduction in power write power.The 9T SRAM cell exhibited the lowest write latency of all the cells tested.Among all the simulated devices, the traditional 6T SRAM cell also showed the highestRSNM value. There was discovered the 8T SRAM cell's WSNM.

SELECTION OF DATABASES TO STORE GEOSPATIAL-TEMPORAL DATA

The proliferation of geospatial-temporal data, driven by the widespread adoption of sensor platforms and the Internet of Things, has escalated the demand for effective data management solutions. In this context, GeoMesa, an open-source toolkit designed to enable comprehensive geospatial querying and analytics in distributed computing systems, plays a pivotal role. GeoMesa seamlessly integrates geospatial-temporal indexing capabilities with databases like Accumulo, HBase, Google Bigtable, and Cassandra, facilitating the storage and management of extensive geospatial datasets. This article addresses the critical need to benchmark and compare the performance of Accumulo and Cassandra when employed as underlying data stores for GeoMesa. By conducting performance tests, we aim to provide valuable insights into the relative strengths and weaknesses of these database systems, thereby aiding decision-makers in selecting the most suitable solution for their specific application requirements. The evaluation includes an in-depth analysis of performance metrics, such as throughput and latency, as well as consideration of system parameters, query density, and data access distribution. It was identified that Accumulo outperforms Cassandra almost in all areas – read latency and resource usage under heavy load and write latency under any load. In turn, Cassandra has lower read latency under low load and CPU usage under heavy load.

Interleaved LDPC Decoding Scheme Improves 3-D TLC NAND Flash Memory System Performance

Although NAND flash memory does a lot of work in effectively using Error Correcting Code(ECC) to reduce Uncorrectable Bit Error Rate(UBER). However, if the Frame Error Rate(FER) is not reduced, the lower UBER cannot effectively reduce the read latency of the flash memory system. This phenomenon is especially evident at the end of the flash memory lifetime, where conventional methods significantly reduce the UBER but not to zero, and the remaining error bits are still evenly distributed throughout the flash memory page, resulting in a significant increase in read latency. In this paper, an interleaved LDPC decoding scheme is proposed. By re-evaluating the flash memory channel during the decoding process, the codewords in the flash memory page are corrected frame by frame, and the problem of high FER is solved at the end of the flash memory lifetime. Compared with the conventional algorithm, the proposed method can reduce the FER by up to 34%, reduce the average decoding iterations by 63.4%, and reduce the read latency by up to 65%.

LDPC Level Prediction Toward Read Performance of High-Density Flash Memories

High-density NAND flash memories have been prevailing in storage systems to achieve large capacities for explosive data. However, they suffer from more severe reliability degradation due to the narrowed margins between threshold voltage states. LDPC codes have been widely applied in high-density flash memories to ensure data reliability. Due to the increased number of cell states, more read voltages are required in reading a flash page correctly. This induces more soft levels to read pages with high bit error rates in LDPC decoding. Read latency is significantly increased in high-density flash memories. To enhance the read performance of high-density flash memories, this paper proposes PreLDPC, an LDPC level prediction approach with fine-grained LDPC reading. The key idea of PreLDPC is to predict the final read level during the early read iteration, thus avoiding unnecessary read-retry latency. From a preliminary study, we observe that after decoding in the first two iterations, the ratio of cells that lie in error-prone area (i.e. adjacent area of two cell states) can be obtained. The ratio is closely related to the final read level for a successful decoding. By exploiting this observation, PreLDPC directly uses the predicted read level for LDPC reading, which could eliminate excessive number of read retries. Furthermore, by exploiting the benefit of fine-grained LDPC reading, this paper further divides the existing integer level (called i-level, e.g. level-1 and level-2) into finer decimal level (called d-level, e.g. level-1.25 and level-1.5), and proposes a fine-grained read method. By combining the prediction method and fine-grained method together, PreLDPC can first estimate the i-level and then perform the read-retry iteration with d-levels to eliminate unnecessary read latency as much as possible. From experimental results of real-world workloads on Disksim with SSD extensions, it is verified that PreLDPC can effectively reduce read latency in high-density flash memories.

Non-gendered pronoun processing: an investigation of the gender non-specific third person singular pronoun ‘TA’ in Chinese

ABSTRACT This study investigated the processing of the Chinese nongendered third-person singular pronoun, “TA,” in a series of self-paced reading experiments. We begin by investigating the perceived appropriateness of TA using a novel implementation of the modified maze task. We then contrasted reading latencies for TA and male- and female-gender pronouns in reference to antecedents with varying stereotypical gender (e.g., occupation terms) and definitional gender (e.g., kinship terms). In our analysis, we assessed several means of operationalizing stereotypical gender information. Optimal model performance was achieved with a continuous measure that accounted for individual differences in gender perception, suggesting the involvement of a probabilistic component. Results for reading latencies and perceived appropriateness of TA support previous findings from discourse analysis that TA is not entirely gender-neutral but rather has nuanced contexts of use in modern Chinese written discourse.

Lightweight Read Reference Voltage Calibration Strategy for Improving 3-D TLC NAND Flash Memory Reliability

Flash memory has gradually become the dominant storage device in the consumer market and data centers since the storage capacity increases and production costs decline. Unfortunately, as the bit density of flash memory increased, the severity of reliability issues has escalated. Read retry is necessary to recover high bit-error-rate flash data; however, read retry requires the flash to perform sequential read operations, which significantly increases read latency. To improve the flash memory read performance, a reliable adaptive optimization strategy for flash memory read reference voltage (RRV) is urgently needed. In this paper, we performed a full range of error characterization tests on three-dimensional (3-D) triple-level cell (TLC) flash memory, focusing on the effects of retention leakage, P/E wear, and interlayer variation on the threshold voltage. Finally, a lightweight flash memory RRV calibration strategy was constructed. The experiment results show that the predicted RRV using the proposed strategy is very close to the actual optimal RRV, reducing the raw bit error rate (RBER) of the same model of flash memory by up to 93.2%.

Channel Modeling and Quantization Design for 3D NAND Flash Memory.

As the technology scales down, two-dimensional (2D) NAND flash memory has reached its bottleneck. Three-dimensional (3D) NAND flash memory was proposed to further increase the storage capacity by vertically stacking multiple layers. However, the new architecture of 3D flash memory leads to new sources of errors, which severely affects the reliability of the system. In this paper, for the first time, we derive the channel probability density function of 3D NAND flash memory by taking major sources of errors. Based on the derived channel probability density function, the mutual information (MI) for 3D flash memory with multiple layers is derived and used as a metric to design the quantization. Specifically, we propose a dynamic programming algorithm to jointly optimize read-voltage thresholds for all layers by maximizing the MI (MMI). To further reduce the complexity, we develop an MI derivative (MID)-based method to obtain read-voltage thresholds for hard-decision decoding (HDD) of error correction codes (ECCs). Simulation results show that the performance with jointly optimized read-voltage thresholds can closely approach that with read-voltage thresholds optimized for each layer, with much less read latency. Moreover, the MID-based MMI quantizer almost achieves the optimal performance for HDD of ECCs.

DNN-based error level prediction for reducing read latency in 3D NAND flash memory

3D NAND Flash memory still suffers from many reliability issues in practice, such as endurance and data retention errors. Meanwhile, due to process variation, pages with different layers show different error characteristics even in the same block. In this paper, we firstly propose a deep neural network-based codeword error level prediction model that can effectively predict the level of codeword errors, and we consider all the main factors that affect the codeword errors, including the P/E cycles and retention time, the location information of the codeword. The new network structure can effectively reduce the weight size by approximately 27% without loss of accuracy compared to traditional neural network. Based on this prediction model, we further propose an optimized scheme to reduce the read latency of the system. The results of the model prediction can help the controller to choose a suitable decoding scheme, thus reducing the overall read latency. Experiments show that the proposed network can predict the error level of the codeword to over 97% accuracy, and also significantly help to improve the average read performance with a maximum latency reduction of 45.3%.

ELDPC: An Efficient LDPC Coding Scheme for Phase-Change Memory

Low read latency, long lifetime, and high storage density have all been demonstrated in phase-change memory (PCM), making it an attractive contender for main memory. However, due to resistance drift per cell caused by long-term storage, data reliability becomes a major challenge. Low-density parity-check (LDPC) codes with improved error correction capability can be used in PCM to reduce bit error rates and thus improve data reliability. More interestingly, when the raw bit error rates (RBER) of various pages in PCM is compared at the same storage time, a considerable gap appears, resulting in high sensing and decoding latency. We propose eLDPC, an efficient LDPC coding scheme for reducing sensing and decoding latency, in this paper. We start with a preliminary experiment, which reveals that there is a significant variation in resistance drifts between adjacent distributions, resulting in a large RBER gap for different pages. Then, using a submatrix of the parity-check matrix to shorten the codeword length, eLDPC is inspired to encode pages with lower RBER. The original bit sequence is separated into even bit sequence (EBS) and odd bit sequence (OBS) for pages with higher RBER. eLDPC is used to encode EBS and OBS independently. By utilizing optimized soft information, EBS and OBS are eLDPC decoded. eLDPC can significantly improve error correction capability of LDPC hard decoding, effectively eliminating soft decoding processes and lowering decoding latency. The results of simulations show that eLDPC can greatly decrease decoding iterations and time.

Memtrade: Marketplace for Disaggregated Memory Clouds

We present Memtrade, the first practical marketplace for disaggregated memory clouds. Clouds introduce a set of unique challenges for resource disaggregation across different tenants, including resource harvesting, isolation, and matching. Memtrade allows producer virtual machines (VMs) to lease both their unallocated memory and allocated-but-idle application memory to remote consumer VMs for a limited period of time. Memtrade does not require any modifications to host-level system software or support from the cloud provider. It harvests producer memory using an application-aware control loop to form a distributed transient remote memory pool with minimal performance impact; it employs a broker to match producers with consumers while satisfying performance constraints; and it exposes the matched memory to consumers through different abstractions. As a proof of concept, we propose two such memory access interfaces for Memtrade consumers -- a transient KV cache for specified applications and a swap interface that is application-transparent. Our evaluation using real-world cluster traces shows that Memtrade provides significant performance benefit for consumers (improving average read latency up to 2.8X) while preserving confidentiality and integrity, with little impact on producer applications (degrading performance by less than 2.1%).