Reactive Processors Research Articles

GALS-HMP

We present a new heterogeneous multiprocessor (GALS-HMP) for the execution of Globally Asynchronous Locally Synchronous (GALS) programming languages. It specifically targets SystemJ GALS language, which extends Java with asynchronous and synchronous concurrency. A SystemJ program is partitioned by a compiler onto data-driven and control-driven parts, which are then allocated for the execution on traditional and reactive processors, which constitute GALS-HMP. The reactive processor is customized to meet the requirements of the control parts of the SystemJ programs. The prototypes developed on an FPGA show significant improvements in code size and execution speed compared to the case of using just traditional processors.

Multithreaded Reactive Programming—the Kiel Esterel Processor

The Kiel Esterel Processor (KEP) is a multithreaded reactive processor designed for the execution of programs written in the synchronous language Esterel. Design goals were timing predictability, minimal resource usage, and compliance to full Esterel V5. The KEP directly supports Esterel's reactive control flow operators, notably concurrency and various types of preemption, through dedicated control units. Esterel allows arbitrary combinations and nesting of these operators, which poses particular implementation challenges that are addressed here. Other notable features of the KEP are a refined instruction set architecture, which allows us to trade-off generality against resource usage, and a Tick Manager that minimizes reaction time jitter and can detect timing over-runs.

STARPro — A new multithreaded direct execution platform for Esterel

Esterel programs have traditionally been compiled to software code for general purpose processors or to hardware netlists. This paper, instead, proposes a reactive processor for the direct execution of Esterel. This intermediate approach offers the same flexibility as software compilation, while at the same time, providing much better code size and execution time. The proposed architecture, called STARPro, is a pipelined, multithreaded, reactive processor that provides native support for the direct execution of Esterel. STARPro manages Esterel threads and their scheduling, and also features a hardware preemption unit to assist the handling of the abort constructs in Esterel. In addition to the proposed architecture, we have also developed a new intermediate format called UCCFGsd (unrolled concurrent control-flow graph with surface and depth) to represent the structure of an Esterel program in our compiler. UCCFGsd closely resembles the Esterel source, and it has also been designed with Esterel hardware support in mind, allowing a straight forward translation into STARPro assembly instructions. We have compared the performance of STARPro against a recent reactive architecture and found an average of 37% speed-up in worst-case reaction times, and 38% in average-case reaction times.

A New Multithreaded Architecture Supporting Direct Execution of Esterel

We propose a fully pipelined, multithreaded, reactive processor called STARPro for direct execution of Esterel. STARPro provides native support for Esterel threads and their scheduling. In addition, it also natively supports Esterel's preemption constructs, instructions for signal manipulation, and a notion of logical ticks for synchronous execution. In addition to the reactive processors, we propose a new intermediate format called unrolled concurrent control-flow graph with surface and depth (UCCFGsd) that closely resembles the Esterel source. A compiler, based on UCCFGsd, has been developed for code generation. We have synthesized STARPro and have carried out a range of benchmarking experiments. Experimental results reveal substantial improvement in performance and code size compared to software compilers. We also excel in comparison to recent reactive architectures, by achieving an average speed-up of 37% in worst-case reaction times and a speed-up of 38% in average-case reaction times. This has been achieved by utilizing fewer hardware resources, while incurring an average code size increase of 40%.

Worst Case Reaction Time Analysis of Concurrent Reactive Programs

Reactive programs have to react continuously to their inputs. Here the time needed to react with the according output is important. While the synchrony hypothesis takes the view that the program is infinitely fast, real computations take time. Similar to the traditional Worst Case Execution Time (WCET), the Worst Case Reaction Time (WCRT) of a program determines the maximal time for one reaction.In this paper, we present an algorithm to determine the WCRT of a program written in the synchronous language Esterel. This value gives an upper bound for the execution time when the program is executed on a reactive processor. Specifically, we consider the execution of the Esterel program on the Kiel Esterel Processor (KEP), a reactive processor that can execute Esterel-like instructions. Here the WCRT directly determines an upper bound on the instruction cycles per logical tick. The WCRT also gives a guideline for the execution time when the Esterel program is compiled to software by a simulation-based approach.We have implemented the WCRT analysis algorithm as part of an Esterel compiler for the Kiel Esterel Processor (KEP) and have measured an accuracy of analysis results of about 22% on average.

Mapping esterel onto a multi-threaded embedded processor

The synchronous language Esterel is well-suited for programming control-dominated reactive systems at the system level. It provides non-traditional control structures, in particular concurrency and various forms of preemption, which allow to concisely express reactive behavior. As these control structures cannot be mapped easily onto traditional, sequential processors, an alternative approach that has emerged recently makes use of special-purpose reactive processors. However, the designs proposed so far have limitations regarding completeness of the language support, and did not really take advantage of compile-time knowledge to optimize resource usage.This paper presents a reactive processor, the Kiel Esterel Processor 3a (KEP3a), and its compiler. The KEP3a improves on earlier designs in several areas; most notable are the support for exception handling and the provision of context-dependent preemption handling instructions. The KEP3a compiler presented here is to our knowledge the first for multi-threaded reactive processors. The translation of Esterel's preemption constructs onto KEP3a assembler is straightforward; however, a challenge is the correct and efficient representation of Esterel's concurrency. The compiler generates code that respects data and control dependencies using the KEP3a priority-based scheduling mechanism. We present a priority assignment approach that makes use of a novel concurrent control flow graph and has a complexity that in practice tends to be linear in the size of the program. Unlike earlier Esterel compilation schemes, this approach avoids unnecessary context switches by considering each thread's actual execution state at run time. Furthermore, it avoids code replication present in other approaches.

Mapping esterel onto a multi-threaded embedded processor

The synchronous language Esterel is well-suited for programming control-dominated reactive systems at the system level. It provides non-traditional control structures, in particular concurrency and various forms of preemption, which allow to concisely express reactive behavior. As these control structures cannot be mapped easily onto traditional, sequential processors, an alternative approach that has emerged recently makes use of special-purpose reactive processors. However, the designs proposed so far have limitations regarding completeness of the language support, and did not really take advantage of compile-time knowledge to optimize resource usage.This paper presents a reactive processor, the Kiel Esterel Processor 3a (KEP3a), and its compiler. The KEP3a improves on earlier designs in several areas; most notable are the support for exception handling and the provision of context-dependent preemption handling instructions. The KEP3a compiler presented here is to our knowledge the first for multi-threaded reactive processors. The translation of Esterel's preemption constructs onto KEP3a assembler is straightforward; however, a challenge is the correct and efficient representation of Esterel's concurrency. The compiler generates code that respects data and control dependencies using the KEP3a priority-based scheduling mechanism. We present a priority assignment approach that makes use of a novel concurrent control flow graph and has a complexity that in practice tends to be linear in the size of the program. Unlike earlier Esterel compilation schemes, this approach avoids unnecessary context switches by considering each thread's actual execution state at run time. Furthermore, it avoids code replication present in other approaches.

Mapping esterel onto a multi-threaded embedded processor

The synchronous language Esterel is well-suited for programming control-dominated reactive systems at the system level. It provides non-traditional control structures, in particular concurrency and various forms of preemption, which allow to concisely express reactive behavior. As these control structures cannot be mapped easily onto traditional, sequential processors, an alternative approach that has emerged recently makes use of special-purpose reactive processors. However, the designs proposed so far have limitations regarding completeness of the language support, and did not really take advantage of compile-time knowledge to optimize resource usage.This paper presents a reactive processor, the Kiel Esterel Processor 3a (KEP3a), and its compiler. The KEP3a improves on earlier designs in several areas; most notable are the support for exception handling and the provision of context-dependent preemption handling instructions. The KEP3a compiler presented here is to our knowledge the first for multi-threaded reactive processors. The translation of Esterel's preemption constructs onto KEP3a assembler is straightforward; however, a challenge is the correct and efficient representation of Esterel's concurrency. The compiler generates code that respects data and control dependencies using the KEP3a priority-based scheduling mechanism. We present a priority assignment approach that makes use of a novel concurrent control flow graph and has a complexity that in practice tends to be linear in the size of the program. Unlike earlier Esterel compilation schemes, this approach avoids unnecessary context switches by considering each thread's actual execution state at run time. Furthermore, it avoids code replication present in other approaches.

HiDRA—A reactive multiprocessor architecture for heterogeneous embedded systems

Embedded systems are typically heterogeneous requiring interacting hardware and software components, are locally synchronous while being globally asynchronous and combine both control and data dominated blocks. Conventional architectures and hardware–software platforms do not directly support such heterogeneity leading to complex design flow and verification process for such systems. This paper presents a new architecture for heterogeneous embedded systems called HiDRA based on multiple reactive processor cores. The architecture supports globally asynchronous locally synchronous systems with a mix of data-dominated and control-dominated behaviors. The reactive processor cores implement Esterel-like computation with architectural support for signal polling, emission and preemption. HiDRA also provides primitives for communication and synchronization between concurrent processes. A low level (concurrent reactive assembly) language has been specified to model embedded applications, which are executable directly on the HiDRA platform. The first implementations with up to four reactive processors have been done on the standard FPGAs. Performance comparison with a typical application realized from system level language ECL reveals significant speedup and reduction in code size.

The Abelian sandpile and related models

The Abelian sandpile model is the simplest analytically tractable model of self-organized criticality. This paper presents a brief review of known results about the model. The Abelian group structure of the algebra of operators allows an exact calculation of many of its properties. In particular, when there is a preferred direction, one can calculate all the critical exponents characterizing the distribution of avalanche-sizes in all dimensions. For the undirected case, the model is related to q → 0 state Potts model. This enables exact calculation of some exponents in two dimensions, and there are some conjectures about others. We also discuss a generalization of the model to a network of communicating reactive processors. This includes sandpile models with stochastic toppling rules as a special case. We also consider a nondashAbelian stochastic variant, which lies in a different universality class, related to directed percolation.

Surface modification and adhesion mechanisms in woodfiber-polypropylene composites

The interfacial adhesion between wood fiber and thermoplastic matrix polymer plays an important role in determining the performance of wood-polymer composites. The objectives of this research were to elucidate the interaction between the anhydride groups of maleated polypropylene (MAPP) and hydroxyl groups of wood fiber, and to clarify the mechanisms responsible for the interfacial adhesion between wood fiber and polypropylene matrix. The modification techniques used were bulk treatment in a thermokinetic reactive processor and solution coating in xylene. FT-IR was used to identify the nature of bonds between wood fiber and MAPP. IGC and wood veneer pull-out test was used to estimate the interfacial adhesion. Mechanical properties of injection molded woodfiber-polypropylene composites were also determined and compared with the results of esterification reaction and interfacial adhesion tests. Confocal Microscopy was employed to observe the morphology at the wood fiber-polypropylene interface, and the dispersion and orientation of wood fiber in the polypropylene matrix, respectively. The effectiveness of MAPP to improve the mechanical properties (particularly the tensile strength) of the composites was attributed to the compatibilization effect which is accomplished by reducing the total wood fiber surface free energy, improving the polymer matrix impregnation, improving fiber dispersion, improving fiber orientation, and enhancing the interfacial adhesion through mechanical interlocking. There was no conclusive evidence of the effects of ester links on the mechanical properties of the composites.