RD53A Chip Research Articles

Evaluation of planar silicon pixel sensors with the RD53A readout chip for the Phase-2 Upgrade of the CMS Inner Tracker

The Large Hadron Collider at CERN will undergo an upgrade in order to increase its luminosity to 7.5 × 1034 cm-2s-1. The increased luminosity during this High-Luminosity running phase, starting around 2029, means a higher rate of proton-proton interactions, hence a larger ionizing dose and particle fluence for the detectors. The current tracking system of the CMS experiment will be fully replaced in order to cope with the new operating conditions. Prototype planar pixel sensors for the CMS Inner Tracker with square 50 μm × 50 μm and rectangular 100 μm × 25 μm pixels read out by the RD53A chip were characterized in the lab and at the DESY-II testbeam facility in order to identify designs that meet the requirements of CMS during the High-Luminosity running phase. A spatial resolution of approximately 3.4 μm (2 μm) is obtained using the modules with 50 μm × 50 μm (100 μm × 25 μm) pixels at the optimal angle of incidence before irradiation. After irradiation to a 1 MeV neutron equivalent fluence of Φeq = 5.3 × 1015 cm-2, a resolution of 9.4 μm is achieved at a bias voltage of 800 V using a module with 50 μm × 50 μm pixel size. All modules retain a hit efficiency in excess of 99% after irradiation to fluences up to 2.1 × 1016 cm-2. Further studies of the electrical properties of the modules, especially crosstalk, are also presented in this paper.

Characterization of the first RD53A triplet modules assembled at IFAE

IFAE is engaged in the production of linear triplet modules for the forthcoming upgrade of the Inner Tracker for the high luminosity phase of the Large Hadron Collider. The pre-production process requires the fabrication of early prototypes (the RD53A chip) to inform the assembly and electrical test methodologies. Module prototypes (also called triplets) include a set of 3 hybrids (sensors connected to readout chips), all of them are mounted in an individual flexible PCB. This document presents the assembly methodologies and main electrical tests results for the first set of 4 modules assembled at IFAE.

Characterization of irradiated RD53A pixel modules with passive CMOS sensors

We are investigating the feasibility of using CMOS foundries to fabricate silicon detectors, both for pixels and for large-area strip sensors. The availability of multi-layer routing will provide the freedom to optimize the sensor geometry and the performance, with biasing structures in poly-silicon layers and MIM-capacitors allowing for AC coupling. A prototyping production of strip test-structures and RD53A compatible pixel sensors was recently completed at LFoundry in a 150 nm CMOS process. This paper will focus on the characterization of irradiated and non-irradiated pixel modules, composed by a CMOS passive sensor interconnected to a RD53A chip. The sensors are designed with a pixel cell of 25 × 100 μm2 in case of DC coupled devices and 50 × 50 μm2 for the AC coupled ones. Their performance in terms of charge collection, position resolution, and hit efficiency was studied with measurements performed in the laboratory and with beam tests. The RD53A modules with LFoundry silicon sensors were irradiated to fluences up to .

Optimization of the 65-nm CMOS Linear Front-End Circuit for the CMS Pixel Readout at the HL-LHC

The linear front-end is the analog processor chosen for the final integration into the pixel readout chip for the high-luminosity upgrade of the CMS experiment at the large hadron collider. The front-end has been included in the RD53A chip, designed by the CERN RD53 collaboration and submitted in 2017. An optimized version of the front-end has been designed, submitted, and tested in the framework of the RD53B developments. The optimization is mainly concerned with the time-walk performance of the front-end and with its threshold tuning capabilities. The article describes in detail such design improvements together with the results from the characterization of a small prototype chip including a 16 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 16 pixel matrix featuring both the RD53A and RD53B versions of the front-end. Test results show a significant reduction, about 10 ns for input signals close to the threshold, of the time-walk in the RD53B front-end, featuring a threshold dispersion smaller than 65 electrons r.m.s. after exposure to a total ionizing dose of 1 Grad of X-rays.

Radiation tolerant, thin, passive CMOS sensors read out with the RD53A chip

The radiation hardness of passive CMOS pixel sensors fabricated in 150nm LFoundry technology is investigated. CMOS process lines are especially of interest for large-scale silicon detectors as they offer high production throughput at comparatively low cost. Moreover, several features like poly-silicon resistors, MIM-capacitors and several metal layers are available which can help enhance the sensor design. The performance of a 100µm thin passive CMOS sensor with a pixel pitch of 50µm at different irradiation levels, 5 × 1015neqcm−2 and 1 × 1016neqcm−2, is presented. The sensor was bump-bonded and read out using the RD53A readout chip. After the highest fluence a hit-detection efficiency larger than 99% is measured for minimum ionising particles. The measured equivalent noise charge is comparable to conventional planar pixel sensors. Passive CMOS sensors are thus an attractive option for silicon detectors operating in radiation harsh environments like the upgrades for the LHC experiments.

Novel 3D Pixel Sensors for the Upgrade of the ATLAS Inner Tracker

The ATLAS experiment will undergo a full replacement of its inner detector to face the challenges posed by the High Luminosity upgrade of the Large Hadron Collider (HL-LHC). The new Inner Tracker (ITk) will have to deal with extreme particle fluences. Due to its superior radiation hardness the 3D silicon sensor technology has been chosen to instrument the innermost pixel layer of ITk, which is the most exposed to radiation damage. Three foundries (CNM, FBK, and SINTEF), have developed and fabricated novel 3D pixel sensors to meet the specifications of the new ITk pixel detector. These are produced in a single-side technology on either Silicon On Insulator (SOI) or Silicon on Silicon (Si-on-Si) bonded wafers by etching both n- and p-type columns from the same side. With respect to previous generations of 3D sensors they feature thinner active substrates and smaller pixel cells of 50 × 50 and 25 × 100 µm2. This paper reviews the main design and technological issues of these novel 3D sensors, and presents their characterization before and after exposure to large radiation doses close to the one expected for the innermost layer of ITk. The performance of pixel modules, where the sensors are interconnected to the recently developed RD53A chip prototype for HL-LHC, has been investigated in the laboratory and at beam tests. The results of these measurements demonstrate the excellent radiation hardness of this new generation of 3D pixel sensors that enabled the project to proceed with the pre-production for the ITk tracker.

A new generation of radiation hard 3D pixel sensors for the ATLAS upgrade

The ATLAS experiment at the Large Hadron Collider (LHC) will replace its inner tracker system to cope with the extreme particle fluence expected after the High Luminosity upgrade of the accelerator (HL-LHC). The 3D silicon sensor technology has been selected as baseline to instrument the innermost layer of the pixel detector in the future ATLAS Inner Tracker (ITk). A new generation of 3D pixel sensors with thin active substrates and small pixel cells of (50×50)μm2 and (25×100)μm2 produced at CNM in Spain, have been interconnected to the RD53A chip, the first prototype of ASIC for the HL-LHC. Performance of these new 3D RD53A modules have been studied before and after uniform proton irradiation up to 1 × 1016neq/cm2, i.e. a particle fluence close to the one expected for the innermost layer of ITk. The first results of the power dissipation and hit efficiency for uniformly irradiated 3D RD53A devices will be presented. These revealed a superior radiation hardness of these novel pixel sensors.

Serial powering in four-chip prototype RD53A modules for Phase 2 upgrade of the CMS pixel detector

Serial powering is the baseline choice for the upgrade of the CMS pixel detector for the High Luminosity LHC. The first results with the four-chip prototype pixel detector modules based on the demonstrator 65nm CMOS technology RD53A chip are presented. The serially powered chain is operated at a constant supply current and the regulation is performed on-chip using a shunt low-dropout regulator (SLDO). Chips on each module are powered in parallel to prevent single-point failures. The SLDO behaviour in the system is presented as well as relevant differences in the behaviour compared to single chips. The noise levels are measured in pixels of a module in a serially powered chain and no increase is observed compared to a single module or the reported noise levels for a single chip.

Module development for the Phase-2 ATLAS ITk Pixel upgrade

For the high luminosity upgrade of the Large Hadron Collider (HL-LHC), the instantaneous luminosity is expected to reach unprecedented values, resulting in about 200 proton-proton interactions in a typical bunch crossing. To cope with the resultant increase in occupancy, bandwidth and radiation damage, the ATLAS Inner Detector will be replaced by an all-silicon system, the Inner Tracker (ITk). The innermost part of ITk will consist of a state-of-the-art pixel detector, with an active area of about 14 m2, which will provide tracking capability up to |η|=4. Detector requirements in terms of radiation hardness and occupancy, as well as thermal performance depend strongly on the distance from the interaction region. Therefore, the innermost layer will feature 3D silicon sensors, due to their inherent radiation hardness and low power consumption, while the remaining layers will employ planar silicon sensors with thickness ranging from 100 μm to 150 μm. All hybrid detector modules will be read out by novel ASICs, implemented in 65 nm CMOS technology and thinned to 150 μm, which will be connected to the silicon sensors using bump bonding. With the recent arrival of the first readout chip prototype, the RD53A chip, prototype modules are being built to study sensor and chip properties, thermal performance, as well as bump bonding yield in lab measurements and beam test campaigns. Irradiation studies are ongoing. The report will present latest results from the module characterization measurements both before and after irradiation.

Performance of Irradiated RD53A 3D Pixel Sensors

The ATLAS experiment at the LHC will replace its current inner tracker system for the HL-LHC era. 3D silicon pixel sensors are being considered as radiation-hard candidates for the innermost layers of the new fully silicon-based tracking detector. 3D sensors with a small pixel size of (50x50) μm2 and (25x100) μm2 compatible with the first prototype ASIC for the HL-LHC, the RD53A chip, have been studied in beam tests after uniform irradiation to 5×1015 neq/cm2. An operation voltage of only 50 V is needed to achieve a 97% hit efficiency after this fluence.

Module and system test development for the Phase-2 ATLAS ITk Pixel upgrade

In the high-luminosity era of the Large Hadron Collider, the instantaneous luminosity is expected to reach unprecedented values, resulting in about 200 proton–proton interactions in a typical bunch crossing. To cope with the resulting increase in occupancy, bandwidth and radiation damage, the ATLAS Inner Detector will be replaced by an all-silicon system, the Inner Tracker (ITk). The innermost part of ITk will consist of a pixel detector, with an active area of about 14 m2. In order to cope with the changing requirements in terms of radiation hardness, power dissipation and production yield, several different silicon sensor technologies will be employed in the five barrel and end-cap layers. With the arrival of the first readout chip prototype, the RD53A chip, the development of hybrid detector modules is starting to address numerous production issues, understanding of which will be crucial for the final design and production of the ITk pixel detector modules. In addition, the new powering scheme is serial which introduces further challenges. A large prototyping program on system test level is ongoing. Components for larger structures with multiple modules, based on the FE-I4 front-end chip, which is currently used in the Pixel detector, were produced and are in assembly and evaluation. The paper will present the latest results from the assembly and characterization of prototype modules as well as the latest evaluation and results of thermo-mechanical prototypes and fully electrical prototypes.

Test results and prospects for RD53A, a large scale 65 nm CMOS chip for pixel readout at the HL-LHC

The CERN RD53 collaboration was founded to tackle the extraordinary challenges associated with the design of pixel readout chips for the innermost layers of particle trackers at future high energy physics experiments. Around 20 institutions are involved in the collaboration, which has the support of both ATLAS and CMS experiments. The goals of the collaboration include the comprehensive understanding of radiation effects in the 65 nm technology, the development of tools and methodology to efficiently design large complex mixed signal chips and, ultimately, the development of a full size readout chip featuring a 400 × 400 pixel array with 50μm pitch. In August 2017, the collaboration submitted the large scale chip RD53A, integrating a matrix of 400 × 192 pixels and embodying three different analog front-end designs. This work discusses the characteristic of the RD53A chip, with some emphasis on the analog processors, and presents the first test results on the pixel array.

Pixel readout chip software emulators for the YARR DAQ system upgrade

The Yet Another Rapid Readout (YARR) system is a DAQ system designed for pixel readout chips including the current generation ATLAS FE-I4 chip and the next generation RD53A chip, which is part of the development of new Pixel detector technology to be implemented in High-Luminosity Large Hadron Collider experiments. YARR utilises a PCI-e FPGA card which acts as a simple gateway to pipe all data from pixel readout chips via the high speed PCI-e connection into the host system’s memory. All data processing is done on a software level in the host CPU(s), utilising a data-driven, multi-threaded, parallel processing paradigm. YARR has recently been upgraded to interface with software emulators of pixel readout chips. These emulators offer many benefits: quick development of DAQ software; expansion of the developer base to users without access to readout hardware; preparation of DAQ software for upcoming readout chips, such as RD53A; implementation of Continuous Integration and unit tests to ensure code quality and maintainability. The design and capabilities of the FE-I4 and RD53A software emulators will be presented.

A synchronous analog very front-end in 65 nm CMOS with local fast ToT encoding for pixel detectors at HL-LHC

This work describes the design, in 65 nm CMOS, of a very compact, low power, low threshold synchronous analog front-end for pixel detectors at HL-LHC . Threshold trimming is avoided using offset compensation techniques. Fast ToT encoding is possible, as the comparator can be turned into a Local Oscillator up to several hundreds MHz. Two small prototypes have been submitted and tested; a X-ray irradiation up to 600 Mrad has been performed. Detailed results in terms of gain, noise, ToT and threshold dispersion are presented. This design will be part of the CHIPIX65 demonstrator and of the RD53A chip.