Raw Bit Error Rate Research Articles

Modeling Retention Errors of 3D NAND Flash for Optimizing Data Placement

Considering 3D NAND flash has a new property of process variation (PV) , which causes different raw bit error rates (RBER) among different layers of the flash block. This paper builds a mathematical model for estimating the retention errors of flash cells, by considering the factor of layer-to-layer PV in 3D NAND flash memory, as well as the factors of program/erase (P/E) cycle and retention time of data. Then, it proposes classifying the layers of flash block in 3D NAND flash memory into profitable and unprofitable categories, according to the error correction overhead. After understanding the retention error variation of different layers in 3D NAND flash, we design a mechanism of data placement, which maps the write data onto a suitable layer of flash block, according to the data hotness and the error correction overhead of layers, to boost read performance of 3D NAND flash. The experimental results demonstrate that our proposed retention error estimation model can yield a R 2 value of 0.966 on average, verifying the accuracy of the model. Based on the estimated retention error rates of layers, the proposed data placement mechanism can noticeably reduce the read latency by 29.8 % on average, compared with state-of-the-art methods against retention errors for 3D NAND flash memory.

Lightweight Read Reference Voltage Calibration Strategy for Improving 3-D TLC NAND Flash Memory Reliability

Flash memory has gradually become the dominant storage device in the consumer market and data centers since the storage capacity increases and production costs decline. Unfortunately, as the bit density of flash memory increased, the severity of reliability issues has escalated. Read retry is necessary to recover high bit-error-rate flash data; however, read retry requires the flash to perform sequential read operations, which significantly increases read latency. To improve the flash memory read performance, a reliable adaptive optimization strategy for flash memory read reference voltage (RRV) is urgently needed. In this paper, we performed a full range of error characterization tests on three-dimensional (3-D) triple-level cell (TLC) flash memory, focusing on the effects of retention leakage, P/E wear, and interlayer variation on the threshold voltage. Finally, a lightweight flash memory RRV calibration strategy was constructed. The experiment results show that the predicted RRV using the proposed strategy is very close to the actual optimal RRV, reducing the raw bit error rate (RBER) of the same model of flash memory by up to 93.2%.

ELDPC: An Efficient LDPC Coding Scheme for Phase-Change Memory

Low read latency, long lifetime, and high storage density have all been demonstrated in phase-change memory (PCM), making it an attractive contender for main memory. However, due to resistance drift per cell caused by long-term storage, data reliability becomes a major challenge. Low-density parity-check (LDPC) codes with improved error correction capability can be used in PCM to reduce bit error rates and thus improve data reliability. More interestingly, when the raw bit error rates (RBER) of various pages in PCM is compared at the same storage time, a considerable gap appears, resulting in high sensing and decoding latency. We propose eLDPC, an efficient LDPC coding scheme for reducing sensing and decoding latency, in this paper. We start with a preliminary experiment, which reveals that there is a significant variation in resistance drifts between adjacent distributions, resulting in a large RBER gap for different pages. Then, using a submatrix of the parity-check matrix to shorten the codeword length, eLDPC is inspired to encode pages with lower RBER. The original bit sequence is separated into even bit sequence (EBS) and odd bit sequence (OBS) for pages with higher RBER. eLDPC is used to encode EBS and OBS independently. By utilizing optimized soft information, EBS and OBS are eLDPC decoded. eLDPC can significantly improve error correction capability of LDPC hard decoding, effectively eliminating soft decoding processes and lowering decoding latency. The results of simulations show that eLDPC can greatly decrease decoding iterations and time.

Edge Word-Line Reliability Problem in 3-D NAND Flash Memory: Observations, Analysis, and Solutions

The 3-D flash memory is gradually becoming the mainstream nonvolatile storage medium due to its high capacity and high performance. However, interlayer interference during 3-D flash programming leads to significant differences in the error characteristics of edge and inner word lines; interlayer interference becomes more pronounced as the number of stacked layers increases, seriously affecting data storage reliability. In this study, many actual tests were conducted on triple-level cell (TLC) and quad-level cell (QLC) flash memory, which are the mainstream storage media in the current consumer market, to obtain the edge and inner word-line threshold voltage data under the interference of different factors, such as retention loss and read disturb; then, the threshold voltage difference between the edge and inner word lines under different conditions was quantitatively analyzed. An edge word-line reliability optimization strategy is proposed based on the read-reference voltage extra offset (RRVEO). Experimental results show that this strategy can reduce the edge word-line raw bit error rate (RBER) by more than 90% and eliminate the reliability difference between inner and edge word lines without significant overhead, thus significantly improving the data storage reliability of flash memory.

Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error Characteristics

3D flash memories have been widely developed to further increase the storage capacity of SSDs by vertically stacking multiple layers. However, this special physical structure brings new error characteristics. Existing studies have discovered that there exist significant Raw Bit Error Rate (RBER) variations among different layers and RBER similarity inside the same layer due to the manufacturing process. These error characteristics would introduce a new data reliability issue. Currently, Low-Density Parity-Check (LDPC) code has been widely used to ensure the data reliability of flash memories. It can provide stronger error correction capability for high RBERs by trading with longer read latency. Traditional LDPC codes designed for planar flash memories do not consider the layer RBER characteristics of 3D flash memories, which may induce sub-optimal read performance. This article first investigates the effect of RBER characteristics of 3D flash memories on read performance and then obtains two observations. On one hand, we observe that LDPC read latencies are largely diverse in different flash layers and increase in diverse speeds along with data retention. This phenomenon is caused by the inter-layer RBER variation. On the other hand, we also compare RBERs between different pages of the same flash layer and observe that read latencies with LDPC codes are quite similar, which is caused by the intra-layer RBER similarity. Then, by exploiting these two observation results, this article proposes a Multi-Granularity LDPC (MG-LDPC) read method to adapt read latency increase characteristics across 3D flash layers. In detail, we design five LDPC decoding engines with varied read level increase granularity (higher level induces higher latency) and assign these engines to each layer dynamically according to prior information, or in a fixed way. A series of experimental results demonstrate that the fixed and dynamic MG-LDPC methods can reduce SSD read response time by 21% and 51% on average, respectively.

A shared page-aware machine learning assisted method for predicting and improving multi-level cell NAND flash memory life expectancy

NAND flash memory is widely used in consumer electronics, personal computers, and enterprise data storage servers. The most prevalent source of flash memory errors is retention errors, which are mainly caused by leakage of charges. It has been observed that inside the chip, some flash memory blocks exhibit greater endurance to the retention errors than others. In an effort to prolong life expectancy, previous studies focus on improving the Raw Bit Error Rate (RBER) metric at page and block levels, without due consideration of the geometry of shared pages. In this paper, the first insight we provide is that groups of shared pages have different RBER values, and should be analyzed separately. We use this insight to construct a machine learning model to predict the blocks which have less endurance, using the characterization data of new unused flash memory chip(s). This is accomplished by extracting location-sensitive and value-sensitive features from the shared pages group, and engineering them into more sophisticated and explainable features. Furthermore, we describe how our proposed prediction model can be used in combination with the existing flash translation layer (FTL) wear-leveling algorithm to increase lifetime. We evaluated the proposed prediction and lifetime improvement method for four different machine learning techniques, among which Support Vector Machine (SVM) achieved superior accuracy up to 85% at a lower computational overhead.

Optimal Program-Read Schemes Toward Highly Reliable Open Block Operations in 3-D Charge-Trap NAND Flash Memory

3-D NAND flash memory with vertically stacked layers has been widely applied benefiting from its large capacities and high performances. Recently, a novel open block operation scheme was proposed for further improvements of the utilization efficiency in large capacity blocks. In this article, reliability issues of the open block operation in 3-D charge-trap (CT) NAND flash memory are studied by focusing on the high raw bit error rates (RBERs) in the last programmed word-line (WL), which is named as the edge WL (EWL). By systematical characterizations, it is concluded that high RBER in the EWL originates from lateral charge migration (LCM) due to the special structure of 3-D CT NAND flash. To suppress the RBER in EWL, we propose the extra read (ER) and extra program (EP) schemes to compensate for the charge loss from LCM. The experimental results show that the RBER of EWL can be reduced by an average of 59.8% and 86.5% after adopting ER and EP schemes, respectively. Furthermore, for the highly reliable open block, we design a targeted low-density parity-check (LDPC) operation process to enhance the correction capability. By using these two methods, experimental results show that the error correction capabilities of the LDPC hard decoding are increased by 1.92 and 4.76 times, respectively.

Resolving the Reliability Issues of Open Blocks for 3-D NAND Flash: Observations and Strategies

While the block size of 3-D NAND flash memory increases with the density and capacity, the raw bit-error rates (RBER) of open blocks could be significantly increased. This article conducts a systematic study over reliability issues caused by open blocks, and reports several new observations. We found that the reliability degradation, due to long open time in writing a block, could happen over all layers in a 3-D NAND block, even after the block is closed. To address the reliability issues of open blocks, this article first proposes to adaptively allocate active blocks to serve write requests based on the workload characteristics for open time reduction. We then propose a partial-block refreshing strategy to alleviate the amplified RBER variations in open blocks and, thus, avoid unnecessary refreshing operations in low-RBER layers. Experimental results show that the proposed method can reduce the RBER by 43% through the reduction of the open time by 28% on average, and reduce the extra write operations for refreshing by 23% on average.

Differential Evolution Algorithm With Asymmetric Coding for Solving the Reliability Problem of 3D-TLC CT Flash-Memory Storage Systems

In recent years, NAND flash memory has been widely used in mobile devices, laptops, desktops, and data center storage systems due to its low-power consumption, high performance, high density, lightweight, shock resistance, and high-reliability natures. However, as the stacked layers and the storage density increase, flash memory also suffers from a higher raw bit error rate (RBER) and shorter lifetime. Observing that reliable cell states suffer from less data retention errors and program disturbance, we propose a differential evolution coding scheme to increase the probability of storing data in more reliable cell states, thereby reducing the RBER. We conducted the experiments over a development platform of SSD storage device with 3D-TLC charge trap (CT) NAND flash memory. The experimental results showed that the proposed differential evolution algorithm with asymmetric coding scheme could averagely reduce RBER by 48.88%, 65.45%, 52.61%, 61.99%, 80.19%, and 33.18% compared with baseline, asymmetric coding algorithm, asymmetric coding scheme with stripe-pattern elimination algorithm, UAC- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula> LC, word-line batch score modulation programming, and SCB schemes.

Read latency decrease schemes based on check node error rate for 3D NAND flash memories

Read retry technique intended to reduce read errors by searching the optimal read voltages and the low density parity check (LDPC) code aimed to correct the reduced read errors are widely used in storage systems to improve reliability of the 3D NAND flash memories. However, the read retry operation and LDPC decoding operation generate long read latency in the data read and recovery process. Here, we propose a check node error rate (CNER) based adaptive-step valley search algorithm (CNER-AVSA) for read retry operations to decrease read latency. CNER-AVSA uses adaptive read voltage moving steps to reduce the read operations required by read retry operations and thus decrease the read latency. To further decrease the read latency, CNER-based invalid-iterations eliminating algorithm (CNER-IEA) used for data recovery is proposed. CNER-IEA decreases the read latency by stopping the read retry operations in advance and eliminating the invalid-iterations in LDPC decoding process. Experimental results show that the proposed CNER-AVSA reduces the raw bit error rate (RBER) of the read errors by up to 78.53 % compared to using default read voltages. The deviations between read voltages searched by CNER-AVSA and the actual truth value of the optimal read voltages are smaller than 25 mV. Implementation results of the CNER-IEA show that the read latency reduces by 43.75 % compared with the conventional data recovery method. Experiment data show that the proposed schemes achieve significant decrease in read errors and read latency.

Optimal read voltages decision scheme eliminating read retry operations for 3D NAND flash memories

Read error increment due to threshold voltage degradation is one of the primary reliability issues of 3D NAND flash memories. Read retry technique which reduces read errors by determining the optimal read voltages (ORVs) is an effective means to solve the problem. However, the extra read operations required by read retry increase the read latency in data read and recovery process. Here, we proposed an ORVs decision scheme without specific read retry operations (ORVD-WRRO) to eliminate the read operations required by read retry and thus decrease the read latency. ORVD-WRRO uses the proposed overlap-error-record error-correcting-code (OER-ECC) to determine the ORVs. Besides, ORVD-WRRO adds ORVs decision and modification operations between read sensing operations and the previous read and decoded data by OER-ECC can be used to determine the subsequent ORVs. Thus, the ORVs of the NAND flash memory can be determined without any extra read operations addition. Experimental results show that the deviations between ORVs determined by the proposed ORVD-WRRO and the true value of the ORVs is smaller than 44 mV and the raw bit error rate (RBER) is reduced to less than 0.0087 which is within the error correction capability of QC-LDPC(8255, 8890). Moreover, the proposed scheme can reduce the read and data recovery latency by 23.21% compared with the conventional scheme.

Temperature Impacts on Endurance and Read Disturbs in Charge-Trap 3D NAND Flash Memories.

Temperature effects should be well considered when designing flash-based memory systems, because they are a fundamental factor that affect both the performance and the reliability of NAND flash memories. In this work, aiming to comprehensively understanding the temperature effects on 3D NAND flash memory, triple-level-cell (TLC) mode charge-trap (CT) 3D NAND flash memory chips were characterized systematically in a wide temperature range (−30~70 °C), by focusing on the raw bit error rate (RBER) degradation during program/erase (P/E) cycling (endurance) and frequent reading (read disturb). It was observed that (1) the program time showed strong dependences on the temperature and P/E cycles, which could be well fitted by the proposed temperature-dependent cycling program time (TCPT) model; (2) RBER could be suppressed at higher temperatures, while its degradation weakly depended on the temperature, indicating that high-temperature operations would not accelerate the memory cells’ degradation; (3) read disturbs were much more serious at low temperatures, while it helped to recover a part of RBER at high temperatures.

Exploiting Resistance Drift Characteristics to Improve Reliability of LDPC-Assisted Phase-Change Memory

Phase-change memory (PCM) as emerging non-volatile memory has attracted more attention and considered as the promising replacement of the main memory. PCM has shown good scalability and high storage density, but data storage reliability has become a challenge and concern. When data are written into PCM cells by a phase transition between amorphous and crystalline, the resistance of each state drifts as the increase of storage time due to structural relaxation. As a result, raw bit error rates (RBER) become higher and higher, severely degrading the data storage reliability (i.e., an important problem in PCM). In this paper, we first find that high error percentage exists between the full amorphous and amorphous states in multilevel cell (MLC) PCM via a preliminary experiment, which is the main factor leading to high RBER. Then, we analyze why this phenomenon exists in PCM from the view of the resistance drift. Finally, by exploiting the resistance drift characteristics, we propose drift compensation and drift-aware LDPC decoding schemes to improve reliability of PCM. Simulation results show that the proposed schemes can significantly reduce the RBER and LDPC decoding iterations.

An Early-Life NAND Flash Endurance Prediction System

NAND flash memory – ubiquitous in today’s world of smart phones, SSDs (solid state drives), and cloud storage – has a number of well-known reliability problems. NAND data contains bit errors, which require the use of error correcting codes (ECCs). The raw bit error rate (RBER) increases with program-erase (P-E) cycling, and the number of P-E cycles the device can withstand before the RBER exceeds the ECC capability is called its endurance . ECC operates on data stored in a sector of NAND, and there is a large variation in the endurance of sectors within a device and across devices, resulting in excessively conservative endurance specifications. This research shows, for the first time, that a sector’s true endurance can be predicted with remarkable accuracy, using a combination of the sector’s location within the device, and measurements taken at the very beginning of life. Real-world data is gathered on millions of NAND sectors using a custom-built test platform. Optimised machine learning classification models are built from the raw data to predict if a sector will pass or fail to a fixed ECC threshold, after a target P-E cycling level has been reached. A novel technique is demonstrated that uses different ECC thresholds for model training and testing, which allows the models to be tuned so that they never misclassify samples that would fail. This eliminates ECC failures and data loss, allowing simpler, less expensive ECC schemes to be used for modern NAND devices. It also enables significant endurance extensions to be achieved.

A Low-Cost Improved Method of Raw Bit Error Rate Estimation for NAND Flash Memory of High Storage Density

Cells wear fast in NAND flash memory of high storage density (HSD), so it is very necessary to have a long-term frequent in-time monitoring on its raw bit error rate (RBER) changes through a fast RBER estimation method. As the flash of HSD already has relatively lower reading speed, the method should not further degrade its read performance. This paper proposes an improved estimation method utilizing known data comparison, includes interleaving to balance the uneven error distribution in the flash of HSD, a fast RBER estimation module to make the estimated RBER highly linearly correlated with the actual RBER, and enhancement strategies to accelerate the decoding convergence of low-density parity-check (LDPC) codes and thereby make up the rate penalty caused by the known data. Experimental results show that when RBER is close to the upper bound of LDPC code, the reading efficiency can be increased by 35.8% compared to the case of no rate penalty. The proposed method only occupies 0.039mm2 at 40nm process condition. Hence, the fast, read-performance-improving, and low-cost method is of great application potential on RBER monitoring in the flash of HSD.

Exploiting Error Characteristic to Optimize Read Voltage for 3-D NAND Flash Memory

3-D NAND flash memory has become increasingly popular nonvolatile storage devices due to large capacity and high performance. With the increase of program/erase (P/E) cycles and retention periods, the threshold voltage distribution of 3-D NAND flash memory is prone to shift such that it is difficult to accurately obtain the read reference voltage (RRV). When reading data, read retry operations perform multiple flash sensing to read bit information correctly, inducing extended read latency. To mitigate the read latency, a method of precisely acquiring the RRV is urgently needed. Using an field-programmable gate array (FPGA) hardware testing platform, this article first studies error characteristics of 3-D triple-level cell (TLC) NAND flash memory with the floating gate (FG) structure, which includes the variations of raw bit error rates (RBERs) in different layers and pages, the variations of block reads under different read modes, and the threshold voltage shifting characteristic. Then, based on these characterizations, this article develops an error characteristic aware RRV acquisition scheme, called ECRRV, to gain optimal RRV by exploiting the least square method. Experimental results show that the proposed scheme can significantly diminish the RBER and block read count.

Retention Correlated Read Disturb Errors in 3-D Charge Trap NAND Flash Memory: Observations, Analysis, and Solutions

3-D NAND flash memory has been attracting much attention owing to its ultrahigh storage density and low bit cost, and it has been widely applied in data centers and mobiles. 3-D triple-level-cell (TLC) NAND flash memory can achieve much larger storage capacity by storing 3 bits in each cell. However, the data reliability issues induced by data retention (DR) and read disturb (RD) greatly limit 3-D TLC NAND applications in hot data storage where the stored data are frequently accessed and RD is more serious. In this article, we first systematically study the retention correlated RD (RCRD) errors in 3-D charge trap (CT) TLC NAND flash memory under various conditions. Error characteristics and underlying mechanisms much different from 2-D NAND flash memory are observed: 1) for RCRD with short retention-after data program, error bits increase due to the negative-shift of program states and 2) for RCRD with long retention-after retention 12 h, error bits can be partially recovered on the contrary due to the charge compensation. We propose schemes of precharge the storage layer (PCSL) and thermally stabilize the storage layer (TSSL) to improve the reliability of 3-D NAND flash memory. By using these two methods, experimental results show that raw bit error rates (RBERs) can be significantly reduced by 30% and 20%, respectively.

Exploiting Asymmetric Errors for LDPC Decoding Optimization on 3D NAND Flash Memory

By stacking layers vertically, the adoption of 3D NAND has significantly increased the capacity for storage systems. The complex structure of 3D NAND introduces more errors than planer flash. To address the reliability issue, low-density parity-check (LDPC) code with a strong error correction capability is now widely applied on 3D NAND flash memory. However, LDPC has long decoding latency when the raw bit error rates (RBER) are high. This is because it needs fine-grained soft sensing between voltage states to iteratively decode the raw data. Multiple sensing voltages are applied on flash cell array to gain necessary information for decoding. In this article, a new sensing level placement scheme with reduced number of sensing levels is proposed. The basic idea for the placement scheme is motivated by three asymmetric error characteristics of flash memory: the asymmetric errors between different states, the asymmetric errors caused by voltage left-shifts and right-shifts and asymmetric errors among layers in a 3D NAND flash block. With awareness of these three types of error characteristics, reduced number of sensing levels are placed to achieve reduced read latency for LDPC decoding while maintaining the error correction capability of LDPC. Experiment analysis shows that the proposed scheme achieves significant performance improvement.

Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with selective refresh

A recent large-scale study revealed that the uncorrectable bit error rates in data center solid-sate drives (SSDs) may fall far below the JEDEC standard recommendations. Here, a new refresh policy is proposed to improve the tolerated raw bit error rate (RBER) based on the observation that (a) a small ratio of SSD units may have a much higher RBER than the rest and (b) the RBER is dominated by the retention error rate. An approach is used to estimate the remaining retention time, i.e., the reliable data storage time, of flash memory pages. This estimation can be performed each time a memory page is read based on the number of detected retention errors and the elapsed time since data was programmed or refreshed. The fact that the estimated remaining retention time is smaller than a maximum time interval before the next page access is an indication that data needs to be refreshed. It is estimated that the tolerated retention RBER can be increased by up to 35× over a storage period of 3 years if the stored data are checked on a monthly basis and refreshed only if necessary. The proposed technique has the ability to adapt the average time between refresh operations to the actual RBER. Maximum refresh time reductions of about 12× are reported as compared to systematic refresh schemes.

Performance of Interleaved Block Codes With Burst Errors

A Gilbert–Elliott channel for symbol errors is considered to analyze the performance of interleaved error correction codes with a fixed block size in the presence of burst errors. The proposed channel model for symbol errors is based on a simplified Gilbert channel for bit errors, which enables direct comparisons of the performance of block codes with different symbol sizes. The autocorrelation function between two erroneous symbols within an interleaved codeword is computed. An exact expression for the codeword-error probability is derived from the symbol-based channel model. A tight lower bound on the codeword-error probability and error floors, which are observed when the average raw bit-error rate is low, are analyzed using the bit-based channel model.