Rate-distortion Optimal Motion Estimation Research Articles

Parallel H.264/AVC Fast Rate-Distortion Optimized Motion Estimation by Using a Graphics Processing Unit and Dedicated Hardware

Heterogeneous systems on a single chip composed of a central processing unit, graphics processing unit (GPU), and field-programmable gate array (FPGA) are expected to emerge in the near future. In this context, the system on chip can be dynamically adapted to employ different architectures for execution of data-intensive applications. Motion estimation (ME) is one such task that can be accelerated using FPGA and GPU for high-performance H.264/Advanced Video Coding encoder implementation. This paper presents an inherent parallel low-complexity rate-distortion (RD) optimized fast ME algorithm well suited for parallel implementations, eliminating various data dependencies caused by a reliance on spatial predictions. In addition, this paper provides details of the GPU and FPGA implementations of the parallel algorithm by using OpenCL and Very High Speed Integrated Circuits (VHSIC) Hardware Descriptive Language (VHDL), respectively, and presents a practical performance comparison between the two implementations. The experimental results show that the proposed scheme achieves significant speedup on GPU and FPGA, and has comparable RD performance with respect to sequential fast ME algorithm.

Novel RD-Optimized VBSME With Matching Highly Data Re-Usable Hardware Architecture

To achieve superior performance, rate-distortion optimized motion estimation (ME) for variable block size (RDO VBSME) is often used in state-of-the-art video coding systems such as the H.264 JM software. However, the complexity of RDO-VBSME is very high both for software and hardware implementations. In this paper, we propose a hardware-friendly ME algorithm called RDOMFS with a novel hardware-friendly rate-distortion (RD)-like cost function, and a hardware-friendly modified motion vector predictor. Simulation results suggest that the proposed RDOMFS can achieve essentially the same RD performance as RDO-VBSME in JM. We also propose a matching hardware architecture with a novel Smart Snake Scanning order which can achieve very high data re-use ratio and data throughout. It is also reconfigurable because it can achieve variable data re-use ratio and can process variable frame size. The design is implemented with TSMC 0.18 μm CMOS technology and costs 103 k gates. At a clock frequency of 63 MHz, the architecture achieves real-time 1920 × 1080 RDO-VBSME at 30 frames/s. At a maximum clock frequency of 250 MHz, it can process 4096 × 2160 at 30 frames/s.

A Fully Scalable Motion Model for Scalable Video Coding

Motion information scalability is an important requirement for a fully scalable video codec, especially for decoding scenarios of low bit rate or small image size. So far, several scalable coding techniques on motion information have been proposed, including progressive motion vector precision coding and motion vector field layered coding. However, it is still vague on the required functionalities of motion scalability and how it collaborates flawlessly with other scalabilities, such as spatial, temporal, and quality, in a scalable video codec. In this paper, we first define the functionalities required for motion scalability. Based on these requirements, a fully scalable motion model is proposed along with tailored encoding techniques to minimize the coding overhead of scalability. Moreover, the associated rate distortion optimized motion estimation algorithm will be provided to achieve better efficiency throughout various decoding scenarios. Simulation results will be presented to verify the superiorities of proposed scalable motion model over nonscalable ones.

Rate-distortion optimal motion estimation algorithms for motion-compensated transform video coding

Motion estimation and compensation is widely used for exploiting temporal correlation within an image sequence. To find motion vectors that lead to high compression, most motion estimation approaches use a source distortion measure, such as mean-square error (MSE) or mean-absolute error (MAE), as a search criterion. When incorporated into a closed-loop motion compensated (MC) transform video coder, these schemes produce noisy motion fields which significantly increase the bit-rates required to represent motion vectors. In view of this problem, this paper presents a rate-distortion optimal motion estimation algorithm. The proposed scheme improves rate performance of the estimated motion field while maintaining the peak signal-to-noise ratio (PSNR) prediction quality of the distortion-based methods, thereby enabling an efficient bit allocation between motion information and transform-coded prediction residuals. For coders in which motion vectors are differentially encoded, the rate-distortion optimization process is formulated as a shortest-path-finding problem. Adopting this framework, we show that the optimal solution for the conventional block-based motion estimation, followed by one-dimensional (1-D) differential coding and Huffman coding, can be obtained by using dynamic programming or the Viterbi algorithm. We propose an effective fast algorithm that closely approximates the optimal performance while requiring considerably less complexity. Our experimental results demonstrate overall gains in the range of 0.3-1.5 dB.

Rate-distortion optimal motion estimation algorithms for motion-compensated transform video coding

Motion estimation and compensation is widely used for exploiting temporal correlation within an image sequence. To find motion vectors that lead to high compression, most motion estimation approaches use a source distortion measure, such as mean-square error (MSE) or mean-absolute error (MAE), as a search criterion. When incorporated into a closed-loop motion compensated (MC) transform video coder, these schemes produce noisy motion fields which significantly increase the bit-rates required to represent motion vectors. In view of this problem, this paper presents a rate-distortion optimal motion estimation algorithm. The proposed scheme improves rate performance of the estimated motion field while maintaining the peak signal-to-noise ratio (PSNR) prediction quality of the distortion-based methods, thereby enabling an efficient bit allocation between motion information and transform-coded prediction residuals. For coders in which motion vectors are differentially encoded, the rate-distortion optimization process is formulated as a shortest-path-finding problem. Adopting this framework, we show that the optimal solution for the conventional block-based motion estimation, followed by one-dimensional (1-D) differential coding and Huffman coding, can be obtained by using dynamic programming or the Viterbi algorithm. We propose an effective fast algorithm that closely approximates the optimal performance while requiring considerably less complexity. Our experimental results demonstrate overall gains in the range of 0.3-1.5 dB.

Predictive RD optimized motion estimation for very low bit-rate video coding

Predictive rate-distortion (RD) optimized motion estimation techniques are studied and developed for very low bit-rate video coding. Four types of predictors are studied: mean, weighted mean, median, and statistical mean. The weighted mean is obtained using conventional linear prediction techniques. The statistical mean is obtained using a finite-state machine modeling method based on dynamic vector quantization. By employing prediction, the motion vector search can then be constrained to a small area. The effective search area is reduced further by varying its size based on the local statistics of the motion field, through using a Lagrangian as the search matching measure and imposing probabilistic models during the search process. The proposed motion estimation techniques are analyzed within a simple DCT-based video coding framework, where an RD criterion is used for alternating among three coding modes for each 8/spl times/8 block: motion only, motion-compensated prediction and DCT, and intra-DCT. Experimental results indicate that our techniques yield very good computation-performance tradeoffs. When such techniques are applied to an RD optimized H.263 framework at very low bit rates, the resulting H.263 compliant video coder is shown to outperform the H.263 TMN5 coder in terms of compression performance and computations simultaneously.