Rapid Thermal Annealing Time Research Articles

Improved RF power performance of InAlN/GaN HEMT by optimizing rapid thermal annealing process for high-performance low-voltage terminal applications

Improved radio-frequency (RF) power performance of InAlN/GaN high electron mobility transistor (HEMT) is achieved by optimizing the rapid thermal annealing (RTA) process for high-performance low-voltage terminal applications. By optimizing the RTA temperature and time, the optimal annealing condition is found to enable low parasitic resistance and thus a high-performance device. Besides, compared with the non-optimized RTA HEMT, the optimized one demonstrates smoother ohmic metal surface morphology and better heterojunction quality including the less degraded heterojunction sheet resistance and clearer heterojunction interfaces as well as negligible material out-diffusion from the barrier to the channel and buffer. Benefiting from the lowered parasitic resistance, improved maximum output current density of 2279 mA⋅mm−1 and higher peak extrinsic transconductance of 526 mS⋅mm−1 are obtained for the optimized RTA HEMT. In addition, due to the superior heterojunction quality, the optimized HEMT shows reduced off-state leakage current of 7 × 10−3 mA⋅mm−1 and suppressed current collapse of only 4%, compared with those of 1 × 10−1 mA⋅mm−1 and 15% for the non-optimized one. At 8 GHz and V DS of 6 V, a significantly improved power-added efficiency of 62% and output power density of 0.71 W⋅mm−1 are achieved for the optimized HEMT, as the result of the improvement in output current, knee voltage, off-state leakage current, and current collapse, which reveals the tremendous advantage of the optimized RTA HEMT in high-performance low-voltage terminal applications.

Microstructure Evolution with Rapid Thermal Annealing Time in (001)-Oriented Piezoelectric PZT Films Integrated on (111) Si.

In our recently published paper (Y.-Y. Wang et al., High performance LaNiO3-buffered, (001)-oriented PZT piezoelectric films integrated on (111) Si, Appl. Phys. Lett. 121, 182902, 2022), highly (001)-oriented PZT films with a large transverse piezoelectric coefficient e31,f prepared on (111) Si substrates were reported. This work is beneficial for the development of piezoelectric micro-electro-mechanical systems (Piezo-MEMS) because of (111) Si's isotropic mechanical properties and desirable etching characteristics. However, the underlying mechanism for the achievement of a high piezoelectric performance in these PZT films going through a rapid thermal annealing process has not been thoroughly analyzed. In this work, we present complete sets of data in microstructure (XRD, SEM and TEM) and electrical properties (ferroelectric, dielectric and piezoelectric) for these films with typical annealing times of 2, 5, 10 and 15 min. Through data analyses, we revealed competing effects in tuning the electrical properties of these PZT films, i.e., the removal of residual PbO and proliferation of nanopores with an increasing annealing time. The latter turned out to be the dominating factor for a deteriorated piezoelectric performance. Therefore, the PZT film with the shortest annealing time of 2 min showed the largest e31,f piezoelectric coefficient. Furthermore, the performance degradation occurred in the PZT film annealed for 10 min can be explained by a film morphology change, which involved not only the change in grain shape, but also the generation of a large amount of nanopores near its bottom interface.

High performance LaNiO3-buffered, (001)-oriented PZT piezoelectric films integrated on (111) Si

Integration of high-performance lead zirconate titanate (PZT) piezoelectric films onto (111) Si substrates is beneficial for the development of piezoelectric micro-electro-mechanical systems (Piezo-MEMS) because of (111) Si's isotropic mechanical properties and desirable etching characteristics. These features will greatly reduce complications in micro-device fabrication and patterning of PZT/Si heterostructures. However, piezoelectric performance of a PZT film is usually dominated by its preferred crystalline orientation, with (001) being superior than (110) and (111). Such a vectorial dependence seriously restricts applications of PZT films grown on (111) Si, which are usually not (001)-textured. In this work, highly (001)-oriented PZT thick films (∼1.5 μm) with a 53/47 Zr/Ti ratio were prepared on (111) Si substrates via a multi-layer buffering technique, i.e., through the use of a (111)Pt/Ti bi-layer and a LaNiO3 buffer layer. The PZT films were sputter-deposited at a low temperature (350 °C) and then crystallized in a (001) texture via a rapid thermal annealing (RTA). The e31,f transverse piezoelectric coefficient was up to ∼11.6 C/m2 for PZT films with a RTA time of 2 minutes. Such an e31,f value is comparable to that of PZT films grown on (100) Si. This work opens up many possibilities for Piezo-MEMS by demonstrating the desirable combination of a large piezoelectricity in (001) PZT with a good patternability of (111) Si.

Influence of rapid thermal annealing time on physical properties of Mg and F co-doped ZnO thin films deposited by radio frequency magnetron sputtering

• Mg-F co-doped ZnO (MFZO) thin films are deposited by magnetron sputtering. • Conductivity of MFZO films increases by 37% after the rapid thermal annealing. • The average visible transmittances of the annealed MFZO films exceed 93%. • The annealed MFZO film achieves a high figure of merit (FOM) of 1.18 × 10-2 Ω-1. • The high-FOM MFZO thin films could be used as transparent conducting films. Transparent conducting oxides are commonly used in flat-panel displays, solar cells, light emitting diodes, and other optoelectronic devices. In this study, transparent conducting Mg and F co-doped ZnO (MFZO) thin films were prepared by using radio frequency magnetron sputtering and a post-deposition rapid thermal annealing (RTA) was carried out at 400°C in vacuum. To study the influence of RTA on structural, electrical, and optical properties of the MFZO thin films, the RTA processing time is varied (0–120 s). X-ray diffraction analysis showed that the co-doping of 3.0 at% Mg and 6.0 at% F did not change the (0 0 2) oriented hexagonal wurtzite structure of the MFZO films, while the RTA process effectively improved its crystal quality. The intensity and full width at half maximum of the (0 0 2) peaks revealed that the MFZO films had the optimum crystallinity at the RTA time of 15–60 s and the largest grain size at the RTA time of 30 s. Under this optimal RTA condition, the electrical conductivity increased by 37%, reaching the optimum Hall mobility of 12.5 cm 2 /Vs, carrier concentration of 3.94 × 10 20 cm −3 , and resistivity of 1.27 × 10 −3 Ω cm. The average total transmittance in the visible region (380 – 780 nm) increased to more than 93% at the RTA duration of 15–60 s, and then decreased for a longer RTA time. The optical band gap, determined from the absorption edge of transmittance using Tauc plot, increased from 3.745 to 3.798 eV after RTA for 30 s. The figure of merit (FOM) of the MFZO film increased by 52% to 1.18 × 10 −2 Ω −1 . Thanks to the use of appropriate dopants and RTA process, this high FOM is much superior to previous research results on MFZO thin films with FOMs ranging from 10 −6 to 10 −3 Ω −1 . This work provides a fast and low-temperature approach to realize high-FOM MFZO thin films to fulfill the requirements of a transparent electrode in optoelectronic devices.

Effect of rapid thermal annealing time on ZnO:F thin films deposited by radio frequency magnetron sputtering for solar cell applications

Effect of rapid thermal annealing time on ZnO:F thin films deposited by radio frequency magnetron sputtering for solar cell applications

Thermal pyrolysis investigation of self-assembled molecular monolayer for defect-free doping in silicon

A thermal pyrolysis method, prior to a conventional rapid thermal annealing (RTA) treatment, was developed for octadecylphoshponic acid (ODPA)-modified Si samples. The thermal pyrolysis could break P–C linkage at 500 °C and release carbon impurities from silicon surfaces, because of its weak bonding energy (∼260 kJ/mol) in ODPA molecules. The results show that large amounts (>60%) of C impurities are successfully eliminated. Hall effect measurements suggest that the electrical activation rate of P dopants rises up to 56.7% from 3.8%, while all C-related defects at 133 meV below the conduction band are excluded. The calculated ionization rate of P dopants is approximately 83%. The resultant ∼17%, assigned to Ci–Ps defects, could be further minimized by extending RTA time. Therefore, it is promising to manufacture defect-free doped Si materials by the thermal pyrolysis, together with RTA treatments.

GaN nanostructures by reactive ion etching: Mask and Maskless approach

GaN nanostructures have been fabricated by reactive ion etching (RIE) with and without mask. The mask comprising of self assembled nanoparticles has been prepared by rapid thermal annealing (RTA) of thin film of Ni deposited on GaN epilayers grown by Metal Organic Vapor Phase Epitaxy (MOVPE). Effect of RTA temperature and time on the morphology of mask has been studied using 5 and 10 nm thick Ni films. Using 5 nm Ni film, a good mask composed of sub 50 nm agglomerated nanoparticles in high density (>1E10 /cm2) was fabricated at 850 °C after 90–120 s of RTA. The samples were subjected to BCl3/Cl2 plasma based inductively coupled plasma RIE (ICP-RIE) process to fabricate the nanostructures. The morphology of the fabricated nanostructures exhibited direct correspondence to the Ni mask used. No etching was observed in material underneath the mask area. Conical nanostructures were fabricated in high density with diameter and height of 100 nm and 150 nm. The size of the nanoparticles was identified as the major limitation to fabricate high aspect one dimensional structures like nanowires using this approach. To overcome this limitation, a novel maskless RIE process has been employed with careful choice of process parameters and nanowires with sub 40 nm diameter and 280–300 nm height were successfully fabricated in high density (∼1E10 /cm2) using GaN epilayers with high dislocation density.

Thin dysprosium oxide films formed by rapid thermal annealing on porous SiC substrate

In this paper, we consider the effect of rapid thermal annealing (RTA) on the properties of Dy2O3 film formed on the surface of a substrate with a por-SiC/SiC structure. The atomic composition of the films under study was analyzed as a function of the RTA time. It is shown that the RTA method makes it possible to obtain thin Dy oxide films with a composition close to the stoichiometric one. In this case, an increase in the RTA time leads to improving the quality of film-substrate interface and increasing the optical transmission of Dy2O3/por-SiC/SiC structure

Fabrication of silver nanoparticles on glass substrate using low-temperature rapid thermal annealing

Metallic nanoparticle-based localized surface plasmon resonance phenomenon is of great interest in the field of solar cells and can increase efficiency via solar energy harvesting in the device due to their light trapping capabilities. In present research, rapid thermal annealing, a modern physical technique, has been employed for the fabrication of silver nanoparticles on glass substrates at lower temperature regime. The rapid thermal annealing is carried at temperatures 200, 250, and 300°C for annealing duration of 5, 10, 15, 20, and 30 min of as-sputtered silver clusters and then kept for natural cooling in inert ambient which has resulted into formation of silver nanoparticles on glass substrate. The surface morphological analysis of the grown silver nanoparticles shows average particle size minimization behavior with increase in rapid thermal annealing up to 15 min duration. Thereafter an increase in average size is observed with rapid thermal annealing time duration up to 30 min for all rapid thermal annealing temperatures. A growth mechanism is suggested to explain observed changes in silver nanoparticles size behavior under rapid thermal annealing conditions. The respective absorption peaks are lying in the wavelength range of 400–500 nm which confirms the formation of silver nanoparticles. The optical study for respective size of silver nanoparticles has also been analyzed and compared with that of theoretical calculations from Mie scattering theory.

Surface chemical structure and doping characteristics of boron-doped Si nanowires fabricated by plasma doping

We investigated the conduction characteristics of plasma-doped Si nanowires (NWs) after various rapid thermal annealing (RTA) times. The plasma doping (PD) process developed a highly-deposited B layer at the NW surface. RTA process controls electrical conductivity by mediating the dopant diffusion from the surface layer. The surface chemical and substitutional states of the B plasma-doped Si NWs were analyzed by x-ray photoelectron spectroscopy (XPS) and Raman spectroscopy. To elucidate the detailed structure of the NWs, we analyzed the change in the optical phonon mode caused by the incorporated B atoms. For this purpose, we examined Fano resonance by the investigation of the asymmetry, line-width, and phonon wavenumber in Raman spectra. The changes in symmetry level of the Raman peak, phonon lifetime, and internal strain were closely related to the number of electrically activated borons, which was drastically increased with RTA time. The change in electrical and optical characterizations related to the doping characteristics of the NWs was investigated using a 4-point probe and terahertz time-domain spectroscopy (THz–TDS). The resistivity of the NWs was 3000 times lower after the annealing process compared to that before the annealing process, which is well consistent with the optical conductivity data. The data provide the potential utility of PD in conformal doping for three-dimensional nanodevices.

(Invited) Pattern and Emissivity Insensitive Dopant Activation and Silicide Contact Formation Annealing in a Hot Wall Rapid Thermal Annealing System

Local temperature non-uniformity during rapid thermal annealing (RTA) is an important contributor to within-die process variations which cause significant problems for advanced complimentary metal-oxide-semiconductor (CMOS) device manufacturing. RTA-induced variations strongly depend on circuit layout patterns and optical properties of exposed materials on the surface of the Si wafers. To reduce the “pattern effect”, a hot wall (furnace-based) RTA approach has been proposed and compared with a conventional cold wall (lamp-based) RTA approach in device manufacturing. Nickel and cobalt silicide formations on implanted single crystalline Si in the source/drain region, and implanted poly-Si word lines of memory devices were studied over wide ranges of RTA temperature and time using a hot wall RTA system, which uses mainly natural convection and conduction through ambient gas. Differences between cold wall (radiant) and hot wall (non-radiant) heating on the silicide formation and dopant profiles are compared. The hot wall RTA resulted in superior process uniformity and repeatability regardless of pattern size and emissivity differences on device wafers. Local metal film thickness variations and its interaction with local temperature non-uniformity during RTA are identified as major contributors for the silicidation process variations such as non-uniformity and non-repeatability.

Effect of Substrate Type on CoSi2 Formation in Rapid Thermal Annealing

Annealing process optimization was performed to achieve low resistivity CoSi2 contacts used in different locations (word line, source, drain and gate regions) of advanced memory devices with various types of Si. The effect of Si type and annealing time on the resulting resistivity of the CoSi2 was investigated over a wide range of annealing temperatures (350 ~ 900oC) and times (60 ~ 300s) using a single wafer furnace-based (hot wall) rapid thermal annealing (RTA) system. The properties (conduction type, dopant, stacking structure and crystallinity) of the Si substrate contacting the Co film had a significant effect on the resulting CoSi2 formation temperature and contact resistance. In general, the CoSi2 formation temperature was reduced with the increase of RTA time. Significant differences in CoSi2 formation temperature was observed from different types of Si. The CoSi2 formation temperature for the source/drain (S/D) of P-type transistors was found to be the lowest. The CoSi2 formation temperature for poly Si, used in cells, was found to be the highest and was the limiting factor in RTA temperature reduction efforts.

Comprehensive Characterization of Dual Implanted Silicon after Electrical Activation Annealing

Formation of low resistivity junctions is essential for fabricating high performance devices with advanced device modes. Significant effort has been expended, industry wide, to develop low resistivity junctions, over the years. However, the understanding of implant activation and implant damage recovery process is not sufficient. Development of noncontact implant residual damage monitoring techniques would be beneficial in process development for advanced node devices. In this study, we have investigated the effect of annealing temperature and time on the sheet resistance (Rs) of dual (P+ 1.0MeV, 4.0 x 1013 cm-2 + B+ 10keV, 3.0 x 1014cm-2) implanted p--Si(100) wafers using a single wafer furnace-based (hot wall) rapid thermal annealing (RTA) system over a wide range of annealing conditions (350-800oC, 60-150s). Room temperature photoluminescence (RTPL) spectra were measured from all wafers under two different excitation wavelengths (650 and 785 nm) for additional clues on electrical properties of pn junctions, which cannot be obtained from the Rs measurements. Multiwavelength (457.9, 488.0 and 514.5 nm) Raman characterization was done on all wafers for additional insights on the degree of residual lattice damage, after RTA, under different conditions. After all on wafer measurements were completed, secondary ion mass spectroscopy (SIMS) dopant (P and B) depth profiling was done to assess dopant diffusion during the annealing process.Rs values showed strong and systematic change with RTA temperature and time, as expected. RTPL spectra also showed large variations in intensity and wavelength distribution corresponding to the RTA temperature and time. Multiwavelength Raman characterization results showed gradual increase of intensity with the RTA temperature. Three regions of different Raman shift values, corresponding to the Si lattice stress and possibly the degree of residual implant damage, were also noted. SIMS P and B depth profiles did not show significant changes. Correlation among characterization results from various techniques and RTA conditions will be presented.

Effect of Substrate Type on CoSi2 Formation in Rapid Thermal Annealing

Low resistivity junctions and contacts are essential for fabricating high performance devices with advanced device nodes. Significant effort has been expended towards the development of low resistivity junctions. However, low resistivity contact formation has not received significant attention. The silicide of choice has been changed from high temperature silicide to low temperature silicide (i.e., WSi → TiSi2 → CoSi2 → NiSi) depending on the allowed maximum process temperature and required minimum line width for the device node. Once the candidate silicide material is chosen for the device node, relatively small improvements in resistivity and small changes in the silicide formation process have been made in recent years, despite silicidation process optimization. This includes fine tuning of silicide formation conditions for types of Si (i.e., doped poly Si, NMOS and PMOS), modifications of process steps and integration schemes. In this study, we have investigated the effect of substrate type on CoSi2 formation in rapid thermal annealing (RTA). The RTA temperature and time sensitivity of the resulting resistivity of the Co2Si contacts with P-doped poly-Si, NMOS source/drain (S/D) and PMOS S/D were investigated for process window determination using a single wafer furnace (hot wall)-based RTA system. The type of Si had a significant effect on the resulting CoSi2 formation temperature and contact resistance was observed. With the increase of RTA time, the CoSi2 formation temperature was reduced and the difference of CoSi2 formation temperature for different Si substrates became larger. Depending on CoSi2 integration schemes (i.e., one step (for all CoSi2 in poly-Si gate and S/D) or two step (one for CoSi2 for poly-Si gate and the other for CoSi2 for S/D)), the CoSi2 formation RTA conditions must be modified. Detailed effects of substrate type on CoSi2 formation and process windows will be reported. Figure 1

(Invited) Pattern and Emissivity Insensitive Dopant Activation and Silicide Contact Formation Annealing in a Hot Wall Rapid Thermal Annealing System

Rapid thermal annealing (RTA) enabled shallow junction formation requires very short time annealing at high temperatures for low thermal budget. RTA is typically done by lamp-based radiant heating. Radiant power from lamp arrays is close-loop controlled to execute the temperature of the Si wafer as programmed. The increase of annealing temperature and the decrease of annealing time are generally required for more aggressive device scaling. However, the use of non-equilibrium radiant heat sources (photon energy from lamp arrays) makes the heating process sensitive to the optical properties of the Si wafers. Local temperature non-uniformity during RTA is considered an important contributor for within-die process variations which cause significant problems for advanced complimentary metal-oxide-semiconductor (CMOS) device manufacturing. RTA-induced variations strongly depend on circuit layout patterns and optical properties of exposed materials on the surface of the Si wafers. This phenomenon is often referred to as “pattern effect” known from the early days of RTA introduction in the semiconductor industry. In efforts to reduce the “pattern effect”, various approaches have been proposed and implemented in device manufacturing. Shielding device patterns from the radiant heat source is a common approach, having limited success. It is done by either placing a dummy wafer on the pattern side of the Si wafer or backside heating. One other common approach is to homogenize the optical properties of the pattern side of Si wafer by either adding an optical absorption layer or dummy patterns. A differential thermal energy control technique is also proposed for pattern effect suppression. Non-radiative heating techniques have been proposed and demonstrated effectiveness of this “pattern effect” suppression. In this paper, various silicide contact formations on implanted single crystalline Si in source/drain region and implanted poly-Si in gate region were studied over wide ranges of RTA temperature and time using a hot wall RTA system which uses mainly natural convection and conduction through ambient gas. Dopant profiles of the silicide and doped Si after silicidation in the hot wall RTA system were characterized. Proposed possible silicide formation and dopant diffusion mechanisms are discussed. Differences between radiant heating and non-radiant heating on the silicide formation and dopant profiles are compared. The pattern and emissivity insensitive dopant activation and silicide contact formation annealing results will be introduced and potential applications of the hot wall RTA technique in advanced CMOS devices will be proposed.

Process Optimization of CoSi2 Formation on P-Doped Poly-Si by Hot Wall-Based Rapid Thermal Annealing

Low resistivity junctions and low resistivity contacts are essential for fabricating high performance devices with advanced device modes. Significant effort has been expended to develop low resistivity junctions, industry wide. However, low resistivity contact formation has not received significant attention, other than changing the silicide of choice, depending on required minimum line width or device node. Once the candidate silicide material is chosen for the device node, relatively small improvement in resistivity has been made in recent years, despite silicidation process optimization which include modifications of process steps and integration schemes. In this study, we have investigated the effect of annealing temperature and time on the resulting resistivity of Co2Si contacts with P-doped poly-Si using a single wafer furnace-based (hot wall) rapid thermal annealing (RTA) system. The hot wall RTA resulted in significantly (>20%) lower Rs, down to 19.6 ohm/sq. from equivalent RTA process using conventional tungsten halogen lamp-based (cold wall) RTA systems over a very wide process window (RTA temperature and time). Secondary ion mass spectroscopy (SIMS) dopant (P) depth profiling results revealed that the P atoms in the CoSi2 film and at the CoSi2/P-doped poly-Si interface, redistribute very differently under different RTA conditions. The same Rs value can be realized by different P profiles resulting from different RTA conditions. To enable contact resistance reduction, P pile-up near the CoSi2/P-doped poly-Si interface for and to suppress P depletion from P-doped poly-Si layer for resistivity reduction, lower temperature RTA for longer times in the hot wall RTA system was found to be beneficial. Wafers with almost identical P depth profiles after CoSi2 formation RTA in the cold wall RTA and the hot wall RTA systems, still showed an Rs difference of ~20%. The wafers annealed in the hot wall RTA system always showed lower Rs values indicating higher P dopant activation in the P-doped poly-Si layer. The difference in wafer heating mechanisms between the cold wall (lamp-based) RTA and the hot wall (furnace-based) RTA may have played an important role in the dopant activation and Rs differences. Hot wall RTA is very promising for realizing the low resistivity contacts required in advanced high performance devices. The simple change of annealing technique may extend the life cycle of CoSi2/P-doped poly-Si contacts. The Rs response surface (as a function of RTA temperature and time) and SIMS depth profiles of P atoms will be presented at the meeting. Figure 1

CIGS absorber preparation by non-vacuum particle-based screen printing and RTA densification

CuIn0.7Ga0.3Se2 (CIGS) thin-films are prepared by the particle-based screen printing technique followed by rapid thermal annealing (RTA) densification. Due to the short RTA time, CIGS absorber remains the ideal stoichiometric ratio originated from the CIGS particles in the coating paste and thus the conventional selenization process is not required. The effects of the particle concentrations of the coating paste, the RTA temperature and normal loading during RTA on the performances of the CIGS thin-films are studied. The film thickness increases with the increase of the particle concentration of the coating paste. The carbon content of the film is nearly zero when the RTA temperature is greater than 650°C. The carrier concentration and Hall mobility of the CIGS film increase when increasing the RTA temperature from 300°C to 650°C. Using the coating paste with a particle concentration of 40wt% for screen printing and a three-step, 250°C solvent removal for 5min, 500°C annealing for 7min and 650°C densification for 3min, 1.97Ncm−2 normal loading RTA process, a p-type chalcopyrite CIGS film with the carrier concentration of 1.23×1015cm−3 and mobility of 26.21cm2V−1s−1 is obtained.

Effects of rapid thermal annealing on the structural and local atomic properties of ZnO: Ge nanocomposite thin films

We have investigated the structural and local atomic properties of Ge nanocrystals (Ge-ncs) embedded ZnO (ZnO: Ge) thin films. The films were deposited by sequential sputtering of ZnO and Ge thin film layers on z-cut quartz substrates followed by an ex-situ rapid thermal annealing (RTA) at 600 °C for 30, 60, and 90 s under forming gas atmosphere. Effects of RTA time on the evolution of Ge-ncs were investigated by x-ray diffraction (XRD), scanning electron microscopy (SEM), hard x-ray photoelectron spectroscopy (HAXPES), and extended x-ray absorption fine structure (EXAFS). XRD patterns have clearly shown that fcc diamond phase Ge-ncs of sizes ranging between 18 and 27 nm are formed upon RTA and no Ge-oxide peak has been detected. However, cross-section SEM images have clearly revealed that after RTA process, Ge layers form varying size nanoclusters composed of Ge-ncs regions. EXAFS performed at the Ge K-edge to probe the local atomic structure of the Ge-ncs has revealed that as prepared ZnO:Ge possesses Ge-oxide but subsequent RTA leads to crystalline Ge structure without the oxide layer. In order to study the occupied electronic structure, HAXPES has been utilized. The peak separation between the Zn 2p and Ge 3d shows no significant change due to RTA. This implies little change in the valence band offset due to RTA.

Rapid thermal annealing induced formation of Ge nanoparticles in ZnO thin films: A detailed SAXS study

In this study, germanium nanoparticles (Ge-np) embedded ZnO multilayered thin films were produced on z-cut quartz and Si substrates by sequential r.f. sputtering of ZnO and d.c. sputtering of Ge targets followed by an ex-situ rapid thermal annealing (RTA) process performed at 600°C for 30, 60, and 90s. Evolution of Ge-np via an RTA process has been investigated in detail especially by using a small angle x-ray scattering (SAXS) technique. X-ray diffraction (XRD) patterns showed that fcc diamond phase Ge-np were successfully formed in c-axis oriented ZnO host. Crystallite sizes of diamond phase Ge-np calculated by the Scherrer formula were in the range of 18–27nm. Analysis of SAXS patterns revealed that optimum RTA time at 600°C to form monodispersed Ge-np is 60s. Moreover, 30s RTA was inadequate for the complete crystallization and segregation of crystalline Ge-np; 90s RTA turned out to be improving the crystallite size as well as deteriorating the isolation of Ge-np possibly by inter diffusion of Ge atoms back to ZnO host. These results suggest that RTA applied under certain conditions is a robust and scalable route to form monodispersed well crystallized Ge-np in ZnO multilayered thin films for various applications.

The effect of ITO/Mo/MoO3 anode multilayer film on efficient hole extraction in MEH–PPV/ZnO NP hybrid solar cells

Acidic PEDOT:PSS anode buffer layers (ABLs) are widely used for improving efficiency in organic-based solar cells. Recently stable P-type metal oxides, such as NiO, MoO3, and V2O5, have been applied for replacing the commonly used acidic PEDOT:PSS ABL because of the difficulty in coating PEDOT:PSS solutions onto electrodes or polymer active layers. This highlights the importance of the fabrication and characterization of various ABLs that affect the efficiency of hole extraction and the blocking of electron backflows. We studied MoO3 ABLs formed by the rapid thermal annealing (RTA) of molybdenum (Mo) in oxygen atmosphere. In particular, we propose the use of an indium tin oxide (ITO)/Mo/MoO3 anode multilayer for efficient hole extraction in bulk heterojunction (BHJ)-structure organic-based solar cells. The formation of Mo and MoO3 thin films was controlled by the RTA time with a fixed annealing temperature of 350°C. We obtained a two-fold improvement in the short circuit current (Jsc) of the device with the ITO/Mo/MoO3 anode multilayer film (AMF), compared to a device with a PEDOT:PSS ABL.