Rapid Prototyping Of Application Specific Signal Processors Research Articles

Managing Latency and Buffer Requirements in Processing Graph Chains

Real-time signal-processing applications for high assurance systems are commonly designed using a processing-graph software architecture. Here we demonstrate the management of latency and buffer requirements in such an architecture—the US Navy’s processing graph method (PGM). By applying recent results in real-time scheduling theory to the subset of PGM employed by the US DARPA rapid prototyping of application-specific signal processors (RASSP) synthetic aperture radar (SAR) benchmark application, we identify inherent real-time properties of nodes in a PGM graph, and demonstrate how these properties can be exploited to perform useful and important system-level analyses such as schedulability analysis, end-to-end latency analysis, and memory requirements analysis. More importantly, we develop relationships between properties such as latency and buffer bounds and show how one may be traded off for the other.

RASSP Enterprise Technologies for SignalProcessor Life-Cycle Support

Enterprise integration technologies are a key contributor to improving time-to-market, cost, and design quality by a factor, which is the goal of the DARPA Rapid Prototyping of Application-Specific Signal Processors (RASSP) program [1]. The Lockheed Martin Advanced Technology Laboratories (ATL) RASSP team developed a productivity improvement model, shown in Fig. 1, that indicates the relative contributions of various RASSP technologies to the overall improvement. Enterprise technologies address the entire 17% enterprise partition, and more than half of the 30% reuse and model-year architecture partition, thus accounting for at least 35% of the overall RASSP productivity improvement. The ATL RASSP approach to implement enterprise systems is to extend commercial technologies so the results are available to a broad base of potential users. Unlike current automation concepts which start at later stages of the development cycle, the RASSP enterprise system supports the entire signal processor life cycle. Core concepts of the enterprise system include: Tools and tool frameworks integrated into an enterprise environment Program execution control through workflows Integrated data management functions Design reuse Concurrent engineering team support Integrated design engineering and manufacturing. The model-year architecture, which enables users to rapidly, efficiently upgrade systems with new technology, is supported in the enterprise system by a robust reuse management system. Manufacturing interface and communication services elements of the enterprise system provide improved concurrent engineering support for distributed product teams. The enterprise system will be provided to commercial and aerospace users as products, including a reusable set of workflows for electronics design, commercial tools supporting the enterprise system environment, and utilities to enable users to customize the RASSP enterprise system for a particular organization or project. The enterprise system development cycle includes four build cycles with increasing capabilities. The ATL team completed the Build 2 implementation in May‘96. This implementation supports the processes associated with detailed hardware/software design, architecture design, and trade-off analyses. It is being used at Lockheed Martin and multiple government sites for benchmarking and evaluation. Results to date indicate >5:1 productivity improvements in the manufacturing interface, and 5–10% improvements in design engineering, which is growing with increasing level of utilization.

The RASSP Program: Origin, Concepts, and Status: An Introduction to the Issue

The Rapid Prototyping of Application Specific Signal Processors (RASSP) program is a multi-year DARPA/Tri-Service initiative intended to dramatically improve the process by which complex digital systems, particularly embedded digital signal processors, are designed, manufactured, upgraded, and supported. This paper reviews the genesis of the RASSP program, considering both the problems that defined the need for the program, and the historical conditions under which it began. The RASSP program is then presented from two viewpoints. The first is programmatic, covering the goals and constraints of the program, and describing the roles of the various program participants. The second is technical, covering the major concepts upon which the developing RASSP approach to design is based and showing how the detailed technical discussions contained in the other papers in this issue of the Journal of VLSI Signal Processing relate to one another and fit into an overall development concept. The paper closes with a review of the status of the program as of this writing (Summer 1996).

Rapid Prototyping of Application-SpecificSignal Processors (RASSP) In-Progress Report

The goal of the DARPA/Tri-Service-sponsored Rapid Prototyping of Application-Specific Signal Processors (RASSP) program is to reduce the cost and time to develop and manufacture signal processors by at least a factor of four. Lockheed Martin Advanced Technology Laboratories‘ (ATL) approach to reaching this goal is based on three thrusts: methodology, model-year architecture, and infrastructure (enterprise). The Advanced Technology Laboratories‘ RASSP team—composed of an alliance of companies—implemented the first baseline RASSP system, which advances today‘s state-of-the-art by a factor of >2X. The Advanced Technology Laboratories‘ RASSP team used the methodology and tools to demonstrate cost and design-cycle improvements on the benchmark virtual proto-type, and developed a hardware/software system that demonstrated first-pass success. Additional developments underway will provide further benefits and will demonstrate 4X improvements in cost and time to market. This paper updates the team‘s progress halfway through the program, and highlights the impact of using the RASSP concepts on the design of a SAR processor, a Navy standard processor upgrade, and a CNI application.

RASSP Methodology Evaluation and Lessons Learned Developing IRST Signal Processor

The development of a real-time infrared search and track (IRST) processing system served as a real-world test of progress toward the fourfold reduction in cycle time expected at the end of the four-year Rapid Prototyping of Application Specific Signal Processors (RASSP) program. This signal processor development tested the effectiveness of the RASSP methodology and processes and provided critical metrics to evaluate the 4X roadmap. Virtual Prototyping, a VHDL technique for validating hardware and software design before building hardware, makes the RASSP top-down methodology unique. This paper describes the 4X roadmap for cycle time improvement, our experiences with virtual prototyping and important lessons learned for improving the methodology.

A case study in the development of multi-media educational material: the VHDL interactive tutorial

While industry and academia have been aware of the need for an intensive study of embedded digital system design, resource constraints, fuzzy objectives, and short-time horizon have handicapped progress. The $150M Rapid Prototyping of Application Specific Signal Processors (RASSP) program is a major DARPA/Tri-Service effort designed to overcome these limitations. This effort has developed a number of new technologies that will lead to dramatically shorter prototyping times and reduced life cycle costs. In a effort to ensure the successful transfer of these new technologies, the RASSP Education and Facilitation (RASSP E&F) program is working to transfer this technology into graduate and undergraduate curricula by developing and transferring educational material. Only by successfully inserting these rapid-prototyping technologies into the curricula and research activities of the university community will the long term benefits of these technologies be realized. To achieve this technology transfer objective, the RASSP E&F program has developed educational material on the key elements of rapid-prototyping of embedded digital systems technology. The result of this effort is a set of educational covering selected topics. In conjunction with IEEE, several of the modules developed by the RASSP E&F program designed to teach students the VHDL language were converted to HTML and linked with the VHDL language reference manual to form a self-paced VHDL interactive tutorial. A demonstration version of this learning tool, currently published by IEEE, is presented.

Model-Year Architectures for Rapid Prototyping

The Rapid Prototyping of Application-Specific Signal Processors (RASSP) program is changing the way engineers design embedded signal processors by providing a process that will reduce by at least a factor of four both the time-to-market and cost, and improve design quality. To achieve these improvements, Lockheed Martin's Advanced Technology Laboratories (ATL) is using a methodology that stresses hardware and software reuse, and model-year architectures that enable interoperability and upgrades through open interface standards. This paper describes ATL's model-year architecture, which defines a framework for reuse to enable low-cost technology upgrades for embedded processors. This approach can be applied to a wide range of military and commercial applications.

VHDL-based rapid system prototyping

The Rapid Prototyping of Application-Specific Signal Processors (RASSP) [1---3] program of the US Department of Defense (ARPA and Tri-Services) targets a 4X improvement in the design, prototyping, manufacturing, and support processes (relative to current practice). Based on a current practice study (1993) [4], the prototyping time from system requirements definition to production and deployment, of multiboard signal processors, is between 37 and 73 months. Out of this time, 25---49 months is devoted to detailed hardware/software (HW/SW) design and integration (with 10---24 months devoted to the latter task of integration). With the utilization of a promising top-down hardware-less codesign methodology based on VHDL models of HW/SW components at multiple abstractions, reduction in design time has been shown especially in the area of hardware/software integration [5]. The authors describe a top-down design approach in VHDL starting with the capture of system requirements in an executable form and through successive stages of design refinement, ending with a detailed hardware design. This hardware/software codesign process is based on the RASSP program design methodology called virtual prototyping, wherein VHDL models are used throughout the design process to capture the necessary information to describe the design as it develops through successive refinement and review. Examples are presented to illustrate the information captured at each stage in the process. Links between stages are described to clarify the flow of information from requirements to hardware.

THE RASSP INTEGRATED SYSTEMS TOOL SET PROVIDES BETTER SYSTEM TRADE‐OFF STUDIES

AbstractThe goal of the ARPA/Tri‐Service‐sponsored Rapid Prototyping of Application Specific Signal Processors (RASSP) program is to reduce development and manufacturing time and cost of signal processors by a factor of four. Lockheed Martin's Advanced Technology Laboratories (ATL) RASSP team has developed an integrated systems engineering tool set. This tool set integrates Ascent Logic's RDD‐100, PRICE Systems parametric cost estimation models, and Management Sciences RAM‐ILS tools. This tool set provides systems engineers with cost and reliability estimation data within a systems engineering tool. This tool set is described and an example of the tool usage provided. The example demonstrates the value of the tool integration. This tool set enables systems engineers to estimate the life‐cycle costs and reliability early in the design process.