Random Weight Change Research Articles

Pipelined Memristive Analog-to-Digital Converter With Self-Adaptive Weight Tuning

Benefiting from area and power efficiency, memristors enable the development of neural network analog-to-digital converter (ADC) to break through the limitations of conventional ADCs. Although some memristive ADC (mADC) architectures have been proposed recently, the current research is still at an early stage, which is mainly on the simulation and requires numerous target labels to train the synapse weights. In this paper, we propose a pipelined Hopfield neural network mADC architecture and experimentally demonstrate that such mADC has the capability of self-adaptive weight tuning. The proposed training algorithm is an unsupervised method originated from the random weight change (RWC) algorithm, which is modified to reduce the complexity of error feedback circuit to make it more hardware friendly. The synapse matrix could be adapted to the 1T1R crossbar array. For an 8-bit two-stage pipelined mADC, the proposed architecture in the simulation could achieve 7.69 fJ/conv FOM, 7.90 ENOB, 0.1 LSB INL, and 0.1 LSB DNL. And the experimental performance only achieves 1.56 pJ/conv FOM, 7.59 ENOB, 0.21 LSB INL, and 0.29 LSB DNL, which is mainly limited by the comparator’s switching time.

Feed-Forward learning algorithm for resistive memories

Resistive memory systems, due to their inherent ability to perform Vector–Matrix Multiplication (VMM), have drawn the attention of researchers to realize machine learning applications with low overheads. In resistive memory systems, each memory cell (synapse/neuron) stores a weight in the form of resistance/conductance value. Memristor-based resistive memory has been widely explored in this regard because of its small size and low power consumption. The inference quality of a neural network depends on how efficiently and accurately the weights are stored in the synapses. The weights are calculated using various training algorithms, like back-propagation (BP), least mean square (LMS), and random weight change (RWC). The training accuracy of existing algorithms is directly related to the algorithm complexity and the time devoted for training. This paper presents a training algorithm that requires an additional set of memristors and a threshold gate for training and achieves an accuracy similar to existing algorithms without using any complex circuitry. The method can update synapse weights in parallel and requires fewer epochs for training an application. Results on experiments with standard benchmarks reveal that the method can achieve an average speedup of 38× as compared to state-of-the-art methods.

OCTAN: An On-Chip Training Algorithm for Memristive Neuromorphic Circuits

In this paper, we propose a hardware friendly On-Chip Training Algorithm for the memristive Neuromorphic circuits (OCTAN). Although the proposed algorithm has a simple hardware like that of the random weight change (RWC) algorithm, it is much more efficient in terms of convergence speed and accuracy. In this algorithm, weights of the circuit are updated individually by a small value and the effect of individual weight update is assessed. If the weight change causes an increase in the error of the network, the weight update is reversed by applying the same change in the reverse direction twice. The usefulness of the proposed algorithm is verified by training some neuromorphic circuits for different applications. Compared to RWC and stochastic least-mean-squares (SLMS) training algorithms, our proposed algorithm needs, on average, $329\times $ fewer epochs to find the minimum error point. Moreover, the accuracy of the networks trained by OCTAN is, on average, about 46% higher than those of RWC and SLMS algorithms. Additionally, a hardware for OCTAN is presented. This hardware provides a speedup of $172\times $ ( $61\times $ ) compared to that of the RWC (SLMS) algorithm. Finally, the impact of PVT (process, voltage, and temperature) variations is studied on the proposed training hardware indicating an average training error increase of less than 3.27% in the presence of variations.

On Learning With Nonlinear Memristor-Based Neural Network and its Replication

Nonlinear memristor-based neural network and a circuit-based learning system is addressed in this work. The weights of the neural network are based on the memristor bridge synapse and the learning architecture is designed in analog–digital mixed circuits by adopting a simple learning algorithm called random weight change algorithm. Though the memristor bridge can be efficiently used as a synapse, it still suffers from nonlinearity in weight programming at its extremes due to the boundary effect of memristors, which is a common phenomenon in most of the nano-devices. In this study, a novel architecture of a modified memristor bridge synapse is proposed that avoids the boundary effect issue by shifting the programming origin to the middle of the linear region. To demonstrate the effectiveness of the proposed method, multilayer neural network along with the end-to-end learning architecture is designed in circuit with nonlinear memristors and tested for several classical learning problems. Simulation results showing successful learning and correct behavior of replicated neural network are presented.

Hybrid no-propagation learning for multilayer neural networks

Abstract A hybrid learning algorithm suitable for hardware implementation of multi-layer neural networks is proposed. Though backpropagation is a powerful learning method for multilayer neural networks, its hardware implementation is difficult due to complexities of the neural synapses and the operations involved in error backpropagation. We propose a learning algorithm with performance comparable to but easier than backpropagation to be implemented in hardware for on-chip learning of multi-layer neural networks. In the proposed learning algorithm, a multilayer neural network is trained with a hybrid of gradient-based delta rule and a stochastic algorithm, called Random Weight Change. The parameters of the output layer are learned using the delta rule, whereas the inner layer parameters are learned using Random Weight Change, thereby the overall multilayer neural network is trained without the need for error backpropagation. Experimental results showing better performance of the proposed hybrid learning rule than either of its constituent learning algorithms, and comparable to that of backpropagation on the benchmark MNIST dataset are presented. Hardware architecture illustrating the ease of implementation of the proposed learning rule in analog hardware vis-a-vis the backpropagation algorithm is also presented.

Spintronic memristor synapse and its RWC learning algorithm

As one of the most widely used memristor models, the spintronic memristor has become a promising candidate for the electronic synapse. Non-volatility, nanoscale geometries, binary data and multi-level information storage make the circuit simpler and consume less electricity. In this study, a new spintronic memristor synaptic circuit is proposed which can realise positive, zero and negative weights successfully. Furthermore, the circuits of the presented synaptic-based neuron and compact neural network are designed and an improved random weight change (RWC) algorithm is proposed. Compared with the traditional RWC algorithm, it has faster training speed and less training error. In addition, the neural network is applied to data prediction, the result of which is closer to real data. Finally, the correctness and effectiveness of the proposed network are verified via a series of computer simulations.

Building cellular neural network templates with a hardware friendly learning algorithm

Abstract A general solution for the construction of Cellular Neural Network (CNN) weights (cloning template) with Random Weight Change (RWC) algorithm is proposed. A target image for each input image is prepared via a sketch or any other kind of image processing technique for learning of Cellular Neural Network templates. A vector of randomly generated small values is added to the original weights and tested upon the input-target image pair. As a result, if the learning error decreases, the weight is taken for learning in the next iteration and updated using the same vector of random values. Otherwise, a new random vector for updating the weights is regenerated. One of the strong benefits of the proposed weight learning method is the simplicity of its learning algorithm and hence a simpler hardware architecture. Moreover the proposed method provides a unified solution to the problem of learning CNN templates without having to modify the original CNN structure and is applicable for all types of CNNs and input images. Successful learning of templates for various image processing tasks using different CNN structures are also demonstrated in this paper.

A Circuit-Based Neural Network with Hybrid Learning of Backpropagation and Random Weight Change Algorithms.

A hybrid learning method of a software-based backpropagation learning and a hardware-based RWC learning is proposed for the development of circuit-based neural networks. The backpropagation is known as one of the most efficient learning algorithms. A weak point is that its hardware implementation is extremely difficult. The RWC algorithm, which is very easy to implement with respect to its hardware circuits, takes too many iterations for learning. The proposed learning algorithm is a hybrid one of these two. The main learning is performed with a software version of the BP algorithm, firstly, and then, learned weights are transplanted on a hardware version of a neural circuit. At the time of the weight transplantation, a significant amount of output error would occur due to the characteristic difference between the software and the hardware. In the proposed method, such error is reduced via a complementary learning of the RWC algorithm, which is implemented in a simple hardware. The usefulness of the proposed hybrid learning system is verified via simulations upon several classical learning problems.

멤리스터 브리지 시냅스 기반 신경망 회로 설계 및 하드웨어적으로 구현된 인공뉴런 시뮬레이션

Implementation of memristor-based multilayer neural networks and their hardware-based learning architecture is investigated in this paper. Two major functions of neural networks which should be embedded in synapses are programmable memory and analog multiplication. Memristor, which is a newly developed device, has two such major functions in it. In this paper, multilayer neural networks are implemented with memristors. A Random Weight Change algorithm is adopted and implemented in circuits for its learning. Its hardware-based learning on neural networks is two orders faster than its software counterpart.

A Circuit-Based Learning Architecture for Multilayer Neural Networks With Memristor Bridge Synapses

Memristor-based circuit architecture for multilayer neural networks is proposed. It is a first of its kind demonstrating successful circuit-based learning for multilayer neural network built with memristors. Though back-propagation algorithm is a powerful learning scheme for multilayer neural networks, its hardware implementation is very difficult due to complexities of the neural synapses and the operations involved in the learning algorithm. In this paper, the circuit of a multilayer neural network is designed with memristor bridge synapses and the learning is realized with a simple learning algorithm called Random Weight Change (RWC). Though RWC algorithm requires more iterations than back-propagation algorithm, we show that a circuit-based learning using RWC is two orders faster than its software counterpart. The method to build a multilayer neural network using memristor bridge synapses and a circuit-based learning architecture of RWC algorithm is proposed. Comparison between software-based and memristor circuit-based learning are presented via simulations.

Application of neuro‐fuzzy techniques to robust speed control of PMSM

PurposeThe purpose of the paper is to find a simple structure of speed controller robust against drive parameter variations. Application of neuro‐fuzzy technique in the controller of PI type creates proper nonlinear characteristics, which ensures controller robustness.Design/methodology/approachThe robustness of the controller is based on its nonlinear characteristic introduced by neuro‐fuzzy technique. The paper proposes a novel approach to neural controller synthesis to be performed in two stages. The first stage consists in training the neuro‐fuzzy system to form the proper shape of the control surface, which represents the nonlinear characteristic of the controller. At the second stage, the PI controller settings are adjusted by means of the random weight change procedure, which optimises the control quality index formulated in the paper. The synthesis is performed using simulation techniques and subsequently the behavior of a laboratory speed control system is validated in the experimental setup. The control algorithms of the system are performed by a microprocessor floating point DSP control system.FindingsThe proposed controller structure with proper control surface created by the neuro‐fuzzy technique guarantees expected robustness.Research limitations/implicationsThe proposed controller was tested on a single machine under well defined conditions. Further investigations are required before any industrial applications can be made.Practical implicationsThe proposed controller synthesis and its results may be very helpful in the robotic system where changing of system parameters is characteristic for many industrial robots and manipulators.Originality/valueThe original method of robust controller synthesis was proposed and validated by simulation and experimental investigations.

Artificial neural network based robust speed control of permanent magnet synchronous motors

PurposeThe aim of the paper is to find a simple structure of speed controller robust against drive parameters variations. Application of artificial neural network (ANN) in the controller of PI type creates proper non‐linear characteristics, which ensures controller robustness.Design/methodology/approachThe robustness of the controller is based on its non‐linear characteristic introduced by ANN. The paper proposes a novel approach to neural controller synthesis to be performed in two stages. The first stage consists in training the ANN to form the proper shape of the control surface, which represents the non‐linear characteristic of the controller. At the second stage, the PI controller settings are adjusted by means of the random weight change (RWC) procedure, which optimises the control quality index formulated in the paper. The synthesis is performed using simulation techniques and subsequently the behaviour of a laboratory speed control system is validated in the experimental set‐up. The control algorithms of the system are performed by a microprocessor floating point DSP control system.FindingsThe proposed controller structure with proper control surface created by ANN guarantees expected robustness.Originality/valueThe original method of robust controller synthesis was proposed and validated by simulation and experimental investigations.

A CMOS feedforward neural-network chip with on-chip parallel learning for oscillation cancellation

The paper presents a mixed signal CMOS feedforward neural-network chip with on-chip error-reduction hardware for real-time adaptation. The chip has compact on-chip weighs capable of high-speed parallel learning; the implemented learning algorithm is a genetic random search algorithm: the random weight change (RWC) algorithm. The algorithm does not require a known desired neural network output for error calculation and is suitable for direct feedback control. With hardware experiments, we demonstrate that the RWC chip, as a direct feedback controller, successfully suppresses unstable oscillations modeling combustion engine instability in real time.

A fast on-line neural-network training algorithm for a rectifier regulator

This paper addresses the problem of deadbeat control in fully controlled high-power factor rectifiers. Improved deadbeat control can be achieved through the use of neural network-based predictors for the input current reference to the rectifier. In this application, online training is absolutely required. In order to achieve sufficiently fast online training, a new random search algorithm is presented and evaluated. Simulation results show that this type of network training yields equivalent performance to standard backpropagation training. Unlike backpropagation, however, the random weight change method can be implemented in mixed digital/analog hardware for this application. The paper proposes a very large-scale integration implementation which achieves a training epoch as low as 8 /spl mu/s.

Identification and control of induction motor stator currents using fast on-line random training of a neural network

Artificial neural networks (ANNs), which have no off-line pretraining, can be trained continually on-line to identify an inverter-fed induction motor and control its stator currents. Due to the small time constants of the motor circuits, the time to complete one training cycle has to be extremely small. This paper proposes and evaluates a new form of the random weight change (RWC) algorithm, which is based on the method of random search for the error surface gradient. Simulation results show that the new form of the RWC, termed continually online trained RWC (COT-RWC), yields performance very much the same as conventional backpropagation with on-line training. Unlike backpropagation, however, the COT-RWC method can be implemented in mixed digital/analog hardware and still have a sufficiently small training cycle time. The paper also proposes a VLSI implementation which completes one training cycle in as little as 8 /spl mu/s. Such a fast ANN can identify and control the motor currents within a few milliseconds and, thus, provide self-tuning of the drive while the ANN has no prior information whatsoever of the connected inverter and motor.