Random Switching Scheme Research Articles

Effects of Random Switching Schemes on the EMI Levels of Conventional and Interleaved Buck Converters for Mobile Devices

This study presents a comprehensive detailed analysis of the effect of five different random modulation switching schemes and their randomness levels on the elector magnetic interference (EMI) of designed simple and interleaved DC-DC buck converters for smartphone applications. The analyzed switching schemes are pulse width modulation (PWM), random pulse width modulation (RPWM), random pulse position modulation (RPPM), random carrier frequency modulation various duty (RCFMVD), and random carrier frequency modulation fixed duty (RCFMFD). The experimental analysis is performed for all aforementioned switching modulation schemes at the switching frequency of 20 kHz and different randomness levels (RL) (30% to 85%). For a fixed RL of 40%, the switching current harmonics/conducted emission (CE) levels are 5–10 dB/11 dBμV and 17 dB/14 dBμV lower for the RCFMVD case when compared to conventional PWM for both simple and interleaved buck-converters, respectively. The observed switching current harmonics and CE levels for interleaved schemes are around 23 dB and 12 dBμV lower when compared to the conventional simple buck converter scheme for the analyzed circuit configurations. The EMI levels decrease with the increase in the randomness levels from 30% to 85% with less variations in the output voltage level. The findings suggest that a interleaved buck converter circuit with the least-independent switching mechanisms and higher randomness is more appropriate for the reduction of both current spikes and CE levels with RCFMFD as the switching modulation scheme.

A 2-GHz 32-bit ROM-based direct-digital frequency synthesizer in 0.13 μm CMOS

A 32-bit read-only memory (ROM)-based direct digital frequency synthesizer with a maximum operating frequency of 2 GHz is presented. The proposed ROM-based design is capable of increasing the operation speed of traditional ROM-based DDFS by eliminating the complex control circuits and adopting a novel pseudo differential ROM. With a 14-bit partially segmented DAC based on Q2 Random Walk switching scheme, the prototype DDFS produces a minimum spurious-free dynamic range of 46.38 dBc up to Nyquist frequency at the clock frequency of 2 GHz. This 0.13 μm CMOS chip occupies an active area of 0.55 mm2 and dissipates 450 mW with a 1.2-V digital supply and 3.3-V analog supply.

이동셀룰러망에서 무선 인지 기반 비협력 동적 주파수 자원 할당 기법

In this paper, we propose uncoordinated dynamic frequency(channel) allocation schemes based on cognitive radio in mobile cellular networks(MCNs). Under the assumptions that mobile base stations are equipped with cognitive radio(CR) function and they construct uncoordinated network, the proposed scheme enables the MCNs by suppression of successive channel switching and management of channel allocation in a dynamic and distributed manner. The proposed scheme is composed of two phase processes. In the first phase, highly orthogonal sequences are generated and assigned to mobile base stations. In the second phase, each mobile base station is allocated a channel according to the pre-assigned orthogonal sequences. Simulation results show that the number of successive spectrum switching is reduced significantly compared with the random switching scheme.

A Flyback Rectifier With Spread Harmonic Spectrum

This paper presents a flyback switch-mode rectifier (SMR) with spread harmonic spectrum. The SMR switching control is conducted by a charge-regulated pulsewidth modulation (PWM) scheme with constant turn-on period. The inherently stable discontinuous conduction mode operation is preserved to yield good line drawn power quality. In voltage loop, a quantitatively designed PI feedback controller is augmented with a robust error cancellation control scheme. Further improved dc output voltage regulation and input power quality performances are achieved under varied operating conditions. In spread harmonic spectrum control, the harmonic spectral properties of the developed flyback SMR are first analyzed. Then, the dedicated random switching scheme is developed to let its switch current harmonic spectrum be dispersedly distributed. In the proposed random switching scheme, the PWM turn-off period is modulated using 1-b binary sequence, pseudo random binary sequence, and 4-b binary sequences. Under randomized harmonic spectrum, the SMR control performances are not sacrificed.

A Direct Digital Frequency Synthesizer With Fourth-Order Phase Domain<tex>$DeltaSigma$</tex>Noise Shaper and 12-bit Current-Steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage /spl Delta//spl Sigma/ interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q/sup 2/ Random Walk switching scheme. The /spl Delta//spl Sigma/ interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage /spl Delta//spl Sigma/ noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-/spl mu/m CMOS technology with active area of 1.11mm/sup 2/ including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm/sup 2/. The total power consumption of the DDFS is 200mW with a 3.3-V power supply.

Analysis and spectral characteristics of a spread-spectrum technique for conducted EMI suppression

Frequency modulation (FM) and random switching methods have been used for reducing conducted electromagnetic interference (EMI) in power converters. Limited theoretical studies and comparisons of these schemes, however, are available. In this paper, a detailed analysis and the spectral characteristics of a random carrier-frequency (RCF) technique for suppressing conducted EMI in an offline switched-mode power supply are presented. The analysis provides a theoretical platform for studying the characteristics of this random switching scheme. The level of randomness is defined for the RCF scheme and varied in the converter example so that the effects on the power spectra can be demonstrated. Theoretical predictions of the spectral characteristics of this scheme are confirmed with measurements. The RCF scheme has been compared with the standard constant-frequency pulsewidth modulation (PWM) scheme and the FM scheme. Comparisons of their spectral performance show that the RCF scheme has better conducted EMI suppression than the FM and standard PWM schemes.

Spectral characteristics of randomly switched PWM DC/DC converters operating in discontinuous conduction mode

This paper addresses a comparative study of the spectral characteristics of four random-switching schemes that apply to the basic pulsewidth-modulation (PWM) DC/DC converters operating in discontinuous conduction mode (DCM). They include randomized pulse position modulation, randomized pulsewidth modulation, and randomized carrier frequency modulation with fixed duty cycle and with fixed duty time, respectively. Mathematical models that characterize the input current and output voltage of the three basic PWM converters operating in DCM are derived. In particular, the effectiveness of spreading the dominant switching harmonics in the input current that normally exist in the standard PWM scheme and the introduction of low-frequency harmonics in the output voltage with respect to the randomness level are investigated. The validity of the models and analyses are confirmed experimentally by using a DC/DC buck converter.

A 14-bit intrinsic accuracy Q/sup 2/ random walk CMOS DAC

In this paper, a 14-bit, 150-MSamples/s current steering digital-to-analog converter (DAC) is presented. It uses the novel Q/sup 2/ random walk switching scheme to obtain full 14-bit accuracy without trimming or tuning. The measured integral and differential nonlinearity performances are 0.3 and 0.2 LSB, respectively; the spurious-free dynamic range is 84 dB at 500 kHz and 61 dB at 5 MHz. Running from a single 2.7-V power supply, it has a power consumption of 70 mW for an input signal of 500 kHz and 300 mW for an input signal of 15 MHz. The DAC has been integrated in a standard digital single-poly, triple-metal 0.5-/spl mu/m CMOS process. The die area is 13.1 mm/sup 2/.