Random Delay Variation Research Articles

Resilient High-Performance Processors with Spare RIBs

Resilience to defects and parametric variations is of the utmost concern for future technology generations. Traditional redundancy to repair defects, however, can incur performance penalties owing to multiplexing. This article presents a processor design that incorporates bit-sliced redundancy along the data path. This approach makes it possible to tolerate defects without hurting performance, because the same bit offset is left unused throughout the execution core. In addition, the authors use this approach to enhance performance by avoiding excessively slow critical paths created by random delay variations. Adding a single bit slice, for instance, can reduce the delay overhead of random process variations by 10 percent while providing fault tolerance for 15 percent of the execution core.

Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route Layout

Dependence of within-die delay variations on power supply voltage (VDD) is measured down to 0.4V. The VDD dependence of the within-die delay variation of manual layout and irregular auto place and route (P&R) layout are compared for the first time. The measured relative delay (=sigma/average) variation difference between the manual layout and the P&R layout decreases from 1.56% to 0.07% with reducing VDD from 1.2V to 0.4V, because the random delay variations due to the random transistor variations dominate total delay variations instead of the delay variations due to interconnect length variations at low VDD.

SRAM Leakage Reduction by Row/Column Redundancy Under Random Within-Die Delay Variation

Share of leakage in total power consumption of static RAM (SRAM) memories is increasing with technology scaling. Reverse body biasing increases threshold voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ), which exponentially reduces subthreshold leakage, but it increases SRAM access delay. Traditionally, when all cells of an SRAM block used to have almost the same delay, within-die variations are increasingly widening the delay distribution of cells even within a single SRAM block, and hence, most of these cells are substantially faster than the delay set for the entire block. Consequently, after the reverse body biasing and the resulting delay rise, only a small number of cells violate the original delay of the SRAM block; we propose to replace them with sufficient number of spare rows/columns of SRAM. Our experiments show that the leakage can be reduced by up to 40% in a 90-nm predictive technology by adding less than ten spare columns to an 8-kB SRAM array for a negligible penalty in delay, dynamic power, and area in the presence of 3% uncorrelated random delay variation.

Packet loss and jitter control for real-time MPEG video communications

Real-time video communication over a packet switching network is subject to packet loss and random delay variation called jitter. For compressed video, packet loss can cause significant performance degradation, and for continuous video regeneration, packet jitter can cause discontinuity and additional packet loss. Therefore, for good reception quality of video, a low jitter and a low loss are required. In this paper, a real-time video transport protocol on top of the UNIX UDP/IP is proposed. To reduce the delay jitter and packet loss effects, the protocol uses new mechanisms of such as selective packet discard, buffering, and constant rate playback for compressed MPEG (Moving Pictures Experts Group) video. Test results over Ethernet and under heavy traffic conditions show satisfactory performance which is unnoticeable from the ideal case.