Random Access Memory Cell Design Research Articles

Design of efficient multilayer RAM cell in QCA framework

PurposeQuantum-dot cellular automata (QCA) is a promising technology, which seems to be the prospective substitute for complementary metal-oxide semiconductor (CMOS). It is a high speed, high density and low power paradigm producing efficient circuits. These days, most of the smart devices used for computing, make use of random access memory (RAM). To enhance the performance of a RAM cell, researchers are putting effort to minimize its area and access time. Multilayer structures in QCA framework are area efficient, fast and immune to the random interference. Unlike CMOS, QCA multilayer architectures can be designed using active components on different layers. Thus, using multilayer topology in the design of a RAM cell, which is not yet reported in the literature can improve the performance of RAM and hence, the computing device. This paper aims to present the modular design of RAM cell with multilayer structures in the QCA framework. The fundamental modules such as XOR gate, 2:1 multiplexer and D latch are proposed here using multilayer formations with the goal of designing a RAM cell with the provision of read, write, set and reset control.Design/methodology/approachAll the modules used to design a RAM cell are designed using multilayer approach in QCA framework.FindingsThe proposed multilayer RAM cell is optimized and has shown an improvement of 20% in cell count, 30% in area, 25% in area latency product and 48.8% in cost function over the other efficient RAM designs with set/reset ability reported earlier. The proposed RAM cell is further analyzed for the fault tolerance and power dissipation.Research limitations/implicationsDue to the multilayer structure, the complexity of the circuit enhances which can be eliminated using simple architectures.Originality/valueThe performance metrics and results obtained establish that the multilayer approach can be implemented in the QCA circuit to produce area efficient and optimized sequential circuits such as a latch, flip flop and memory cells.

Optimal design of RAM cell using novel 2:1 multiplexer in QCA technology

Purpose Quantum-dot cellular automata (QCA) has attracted computer scientists as new emerging nanotechnology for replacement the current CMOS technology because it has unique characteristics such as high frequency, extremely small feature size and low power consumption. The main building blocks in QCA are the majority gate and inverter so any Boolean function can be represented using these gates. Many important circuits were the target for implemented in this technology in an optimal form, such as random-access memory (RAM) cell. QCA-RAM cells were introduced in literature with different forms but most of them are not optimized enough. This paper aims to demonstrate QCA inherent capabilities that can facilitate the design of many important gates such as the XOR gate and multiplexer (MUX) without following any Boolean function to get an optimum design in terms of complexity and delay. Design/methodology/approach In this paper, a novel structure of QCA-MUX in an optimal form will be used to design two unique structures of a RAM cell. The proposed RAM cells are the lowest cost required compared with different counterparts. The presented RAM cells used a new approach that follows the new suggested block diagram. The presented circuits are simulated and tested with QCADesigner and QCAPro tools. Findings The comparison of the proposed circuits with the previously reported in the literature show noticeable improvements in speed, area, and the number of cells. The cost function analysis results for the proposed RAM cells show significant improvement compared to older circuits. Originality/value A novel structure of QCA-MUX in an optimal form will be used to design two unique structures of a RAM cell.

HEMT Based 6T Static Random Access Memory Cell Design for High Speed Applications

HEMT Based 6T Static Random Access Memory Cell Design for High Speed Applications

Simple Noise Margin Model for Optimal Design of Unipolar Thin-Film Transistor Logic Circuits

The noise margin (NM) of an inverter is an important feature for the operation stability of the digital circuits. Owing to their simple structure, easy processes, and relatively high gain, the unipolar zero-VGS-load logic design is widely used for implementation of digital circuits in various thin-film transistor (TFT) technologies. In this paper, a simple NM model clarifying the relationship between the NM and electrical/device parameters is developed for the zero-VGS-load inverter. The model is verified by circuit simulations, and is capable of providing a useful guideline for optimal design of unipolar TFT logic circuits. Finally, the application of the derived model in a static random access memory cell design is discussed.

Lateral phase change random access memory cell design for low power operation

In this paper, we present a novel lateral cell design for phase change random access memory (PCRAM) that features an improved thermal management to efficiently reduce the current consumption during reset operation. Simulation, fabrication and electrical characterization results of the lateral concept are presented.