RAM Architecture Research Articles

Enhancing fault tolerance in QCA-based RAM cells: A USE clock-driven approach with a novel majority voter

CMOS IC technology is encountering limitations due to fabrication challenges, matching characteristics, and the pursuit of miniaturization. These constraints have prompted the exploration of alternative technologies to cater to the demands of the nanoscale realm. Quantum Dot Cellular Automata (QCA) has emerged as a promising candidate for implementing digital systems at the nanoscale. However, given the nascent stage of QCA technology, the risk of defects during fabrication in the nano-regime is a significant concern. Consequently, the development of fault-tolerant circuits and systems becomes pivotal for the practical realization of this technology. In this study, we introduce a fault-tolerant 3-input majority voter (FT-MV3) designed to achieve 100% fault tolerance against single-cell omission and additional-cell defects. We also assess the fault tolerance of this design in the presence of other fabrication defects. Furthermore, our study includes an energy dissipation analysis of the proposed design. Additionally, we present layout designs for fault-tolerant RAM cells, both with and without the Universal, Scalable, and Efficient (USE) clocking scheme. Our findings demonstrate that the USE-based RAM cell design exhibits an impressive fault tolerance of 95.52% against single-cell omission defects, making it a robust choice for the implementation of reliable RAM architectures.

Enhancing FPGAs with Magnetic Tunnel Junction-Based Block RAMs

While plentiful on-chip memory is necessary for many designs to fully utilize an FPGA’s computational capacity, SRAM scaling is becoming more difficult because of increasing device variation. An alternative is to build FPGA block RAM (BRAM) from magnetic tunnel junctions (MTJ), as this emerging embedded memory has a small cell size, low energy usage, and good scalability. We conduct a detailed comparison study of SRAM and MTJ BRAMs that includes cell designs that are robust with device variation, transistor-level design and optimization of all the required BRAM-specific circuits, and variation-aware simulation at the 22nm node. At a 256Kb block size, MTJ-BRAM is 3.06× denser and 55% more energy efficient and its F max is 274MHz, which is adequate for most FPGA system clock domains. We also detail further enhancements that allow these 256 Kb MTJ BRAMs to operate at a higher speed of 353MHz for the streaming FIFOs, which are very common in FPGA designs and describe how the non-volatility of MTJ BRAM enables novel on-chip configuration and power-down modes. For a RAM architecture similar to the latest commercial FPGAs, MTJ-BRAMs could expand FPGA memory capacity by 2.95× with no die size increase.

Modular Switched Multiported SRAM-Based Memories

Multiported RAMs are essential for high-performance parallel computation systems. VLIW and vector processors, CGRAs, DSPs, CMPs, and other processing systems often rely upon multiported memories for parallel access. Although memories with a large number of read and write ports are important, their high implementation cost means that they are used sparingly. As a result, FPGA vendors only provide dual-ported block RAMs (BRAMs) to handle the majority of usage patterns. Furthermore, recent attempts to create FPGA-based multiported memories suffer from low storage utilization. Whereas most approaches provide simple unidirectional ports with a fixed read or write, others propose true bidirectional ports where each port dynamically switches read and write. True RAM ports are useful for systems with transceivers and provide high RAM flexibility; however, this flexibility incurs high BRAM consumption. In this article, a novel, modular, and BRAM-based switched multiported RAM architecture is proposed. In addition to unidirectional ports with fixed read/write, this switched architecture allows a group of write ports to switch with another group of read ports dynamically, hence altering the number of active ports. The proposed switched-ports architecture is less flexible than a true-multiported RAM where each port is switched individually. Nevertheless, switched memories can dramatically reduce BRAM consumption compared to true ports for systems with alternating port requirements. Previous live-value-table (LVT) and XOR approaches are merged and optimized into a generalized and modular structure that we call an invalidation-based live-value-table (I-LVT). Like a regular LVT, the I-LVT determines the correct bank to read from, but it differs in how updates to the table are made; the LVT approach requires multiple write ports, often leading to an area-intensive register-based implementation, whereas the XOR approach suffers from excessive storage overhead since wider memories are required to accommodate the XOR-ed data. Two specific I-LVT implementations are proposed and evaluated: binary and thermometer coding. The I-LVT approach is especially suitable for deep memories because the table is implemented only in SRAM cells. The I-LVT method gives higher performance while occupying fewer BRAMs than earlier approaches: for several configurations, BRAM usage is reduced by greater than 44% and clock speed is improved by greater than 76%. The I-LVT can be used with fixed ports, true ports, or the proposed switched ports architectures. Formal proofs for the suggested methods, resources consumption analysis, usage guidelines, and analytic comparison to other methods are provided. A fully parameterized Verilog implementation is released as an open source library. The library has been extensively tested using Altera’s EDA tools.

IMPLEMENTATION OF MIDDLE PRODUCT ALGORITHM ON LINEAR PROCESSOR ARRAYS

This paper presents the design, implementation and performance evaluation of the linear processor array accelerator for matrix multiplication. We call it matrix multiplication processor (MMP). The MMP is composed of n processing elements (PEs) connected in a chain, distributed memory, and dedicated address generator unit (AGU) to generate memory addresses. By using this approach, address generation does not increase the processing time. The AGU is one major difference in the proposed architecture compared to graphics processing units (GPUs) that use ALUs to create addresses. MMP is based on FPGA technology since this circuits possess extreme degree of parallelism and ability to customize the RAM and data path architecture to the computation. We have considered performance metrics of the proposed architecture in the sense of number of PEs, execution time, speedup, efficiency and gain factor. We have implemented AGU and PE in Xilinx Spartan 2E FPGAs using ISE 9.01 as a software tool. We compare our design with respect to the execution time, number of PEs, AT measure, speedup and efficiency with other solutions proposed in the literature.

Bringing WDM Into Optical Static RAM Architectures

Optical RAM appears to be the alternative approach towards overcoming the “Memory Wall” of electronics, suggesting use of light in RAM architectures to enable ps-regime memory access times. In this communication we take advantage of the wavelength properties of optical signals to present new architectural perspectives in optical RAM structures by introducing the WDM principles in the storage area. To this end, we report on a 4 × 4 WDM optical RAM bank architecture that exploits a novel SOA-based multi-wavelength Access Gate (WDM-AG) and a dual wavelength SOA-based SET-RESET All-Optical Flip Flop (AOFF) as fundamental building blocks. The WDM-AG enables simultaneous random access to a 4-bit optical word encoded in 8 different wavelengths, allowing for the four AOFFs of each RAM row to effectively share the same Access Gate. The scheme is shown to support a 10 Gbit/s operation for the incoming 4-bit data streams, with a power consumption of 15 mW/Gbit/s for the WDM-AG and 120 mW/Gbit/s for the AOFFs. The proposed optical RAM architecture reveals that exploiting the WDM capabilities of optical components can lead to RAM bank implementations with smarter column/row encoders/decoders, increased circuit simplicity, reduced number of active elements and associated power consumption, while enabling for re-configurability in optical cache mapping.

FPGAs, Programming Models, and Kit Cars

The degree of parallelism and ability to customize the RAM and data path architecture to the computation have enabled FPGAs to replace custom ASIC chips in many designs. Teams of highly skilled engineers crafting HDL code are the Formula-1 teams of the FPGA world, optimizing data paths from the thousands of programmable elements in an FPGA.

Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM)

Because of its high storage density with superior scalability, low integration cost and reasonably high access speed, spin-torque transfer random access memory (STT RAM) appears to have a promising potential to replace SRAM as last-level on-chip cache (e.g., L2 or L3 cache) for microprocessors. Due to unique operational characteristics of its storage device magnetic tunneling junction (MTJ), STT RAM is inherently subject to a write latency versus read latency tradeoff that is determined by the memory cell size. This paper first quantitatively studies how different memory cell sizing may impact the overall computing system performance, and shows that different computing workloads may have conflicting expectations on memory cell sizing. Leveraging MTJ device switching characteristics, we further propose an STT RAM architecture design method that can make STT RAM cache with relatively small memory cell size perform well over a wide spectrum of computing benchmarks. This has been well demonstrated using CACTI-based memory modeling and computing system performance simulations using SimpleScalar. Moreover, we show that this design method can also reduce STT RAM cache energy consumption by up to 30% over a variety of benchmarks.

Architectures for a quantum random access memory

A random access memory, or RAM, is a device that, when interrogated, returns the content of a memory location in a memory array. A quantum RAM, or qRAM, allows one to access superpositions of memory sites, which may contain either quantum or classical information. RAMs and qRAMs with $n$-bit addresses can access ${2}^{n}$ memory sites. Any design for a RAM or qRAM then requires $O({2}^{n})$ two-bit logic gates. At first sight this requirement might seem to make large scale quantum versions of such devices impractical, due to the difficulty of constructing and operating coherent devices with large numbers of quantum logic gates. Here we analyze two different RAM architectures (the conventional fanout and the ``bucket brigade'') and propose some proof-of-principle implementations, which show that, in principle, only $O(n)$ two-qubit physical interactions need take place during each qRAM call. That is, although a qRAM needs $O({2}^{n})$ quantum logic gates, only $O(n)$ need to be activated during a memory call. The resulting decrease in resources could give rise to the construction of large qRAMs that could operate without the need for extensive quantum error correction.

A modified architecture for high-density MRAM

This paper modifies the magnetic RAM (MRAM) architecture by removing a current rectifier per cell without sacrificing performance. A read operation of stored data is maintained by introducing a simple concept of"virtual ground" of operational amplifier. The modified MRAM design offers a reduced element area and therefore achieves an over tenfold improvement in storage density. The proposed architecture has been proven operable by an engineering experiment

Data reordering converter: an interface block in a linear chain of processing arrays

This paper addresses the problem of hardware synthesis of data reordering converter intended to reorganize the layout of transferred data between various processing stages (components) with different I/O format requirements. The proposed design is based on two objectives: (a) fixed bandwidth to main memory, and (b) scalability to higher performance without increasing main-memory bandwidth. The data reordering converter involves two address transformators and an array of dual-port RAMs. The use of distributed dual-port RAM architecture provides several benefits. First, to exploits parallelism, second, to achieve very high-speed data transfer, and third, to allow random access to data elements within the stream. We outline a new architecture for interfacing processing stages in a linear chain, which operate in a pipeline-parallel fashion that trades speed advantages of systolic/processor arrays with area advantages of high wire organizations. An implementation, in VLSI, of address transformators is described, and shown why data reordering converter is useful in designing special purpose high-performance computing for embedded digital signal processing applications.

Hardware implementation of RAM neural networks

This work describes an alternative technique for hardware and software implementation of RAM-based Boolean neural networks, which describes neurons using the VHDL language. An example of application consisting of the classification problem of the British mail scanned address is attended with a RAM architecture presenting (340 x 12)-input neurons. The weights of each neuron are represented by its truth table and described using simple logic gates (AND, OR, and NOT), aiming to make possible the network logic minimisation and its hardware implementation by the ALTERA MAX + PLUS II fast prototyping package (Altera, 1992). The developed software tool allows the specification and training of the network. Then, its VHDL description is generated to be interpreted and minimised by the ALTERA EPLD design system. If it is not necessary to have high-speed processing or if pre-processing phases are needed, the ANN can be implemented in software. The software strategy makes use of the direct translation of the VHDL description into a simplified C language code. Once the user has specified and taught the network, this approach makes possible automatic prototyping of RAM neural networks in software and hardware.

A modified TRAM architecture

This paper modifies the tree RAM (TRAM) architecture (Jarwala and Pradhan, 1988) of multimegabit dynamic random access memories using a tree-star (TS) interconnection topology. The modified TS-RAM design offers a reduced access time and an improved yield for the proposed TS-RAM architecture. We also propose an improved built-in self test (BIST) approach for the architecture.

A BIST ram architecture with parallel testing in a microprogram rom

Abstract Symmetrically simple test patterns for parallel testing of row/column pattern‐sensitive faults in RAMs are proposed in this paper. Based on the concept of the maximum leakage current among the RAM cells, the worst case testing becomes the critically efficient method for RAM testing. Due to the simplicity of generating test patterns, we can implement a BIST RAM with test procedures stored in a microprogram ROM to reduce the cost and time of testing. The test complexity of row/column pattern‐sensitive faults is reduced to O(N) in an N bits RAM as compared with O(N3/ 2) of [1].

Superconductor-semiconductor memories

The authors describe new types of hybrid superconductor-semiconductor RAMs which utilize the current switches in superconductive electronics to remove important constraints on the design of semiconductor memories and achieve performances attainable by the individual technologies separately. They focus on a voltage word line RAM architecture and illustrate the basic designs in terms of a low-T/sub c/ Josephson-CMOS technology. They discuss the design of interface circuits, word-line drivers, memory cells, and fluxoelectronic current sensing of bit lines. Current projections for 4 K operation indicate that sub-nanosecond 64-kb RAMs using a 0.8- mu m CMOS technology are possible. Extensions of this design to high-T/sub c/ superconductor-CMOS circuits operating at 77 K are briefly discussed. >

Redundancy effect on yield of binary tree RAMs

Recently, a radically new RAM architecture was proposed by Jarwala and Pradhan [10] called TRAM architecture. A 64M version of this architecture is being prototyped by a DRAM manufacturer in Japan. The yield sensitivity of this binary Tree Dynamic RAMs (TRAMs) at variations in tree-depth and redundancy level is investigated in this article. It is analyzed not only the yield of all good chips, but also the probability of generating partially good chips. To this purpose a new stochastic yield model, overcoming the drawbacks of the existing ones, is used. The model is a straightforward one and easy to use in parametric studies of chip's yield versus redundancy level and reconfiguration strategies.

A RAM architecture for concurrent access and on chip testing

A novel RAM architecture supporting concurrent memory access and on chip testing (CMAT) is proposed. A large-capacity memory chip is decomposed into test neighborhoods (TNDs), each of which is tested independently. When there are data stored in a TND, the data are saved into a buffer before testing the TND, and the TND's contents are restored using buffered data after testing the TND. If an external request is not made to the TND, the request can be directed to the addressed memory cells. Otherwise, the buffered data can be loaded back into the TND, or the request is detoured to a corresponding buffer. By deriving an analytical model, the performance penalty and hardware overhead of the CMAT architecture are shown to be very small. >

Yield optimization in large RAM's with hierarchical redundancy

The authors present and analyze large RAM architectures with hierarchical redundancy and determine the optimal redundancy organization for yield enhancement. A two-level redundancy scheme is used for defect tolerance, and the defect distribution is modeled using the compounded Poisson model. The tree random access memory (TRAM), which has been proposed as a design methodology for future multimegabit memories (N. Jarwala et al., 1988) is considered as an example for modeling and optimization. The results show that the two-level hierarchical redundancy approach, with spare bit and word lines within memory quadrants, and additional spare modules for global sparing, along with redundant interconnections can efficiently provide defect tolerance and viable yields for future generations of high-density dynamic random access memories.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An efficient built-in self testing for random-access memory

The authors propose a test algorithm for pattern-sensitive faults in large-size RAM with high circuit density. The algorithm tests an n-bit RAM in 195 square root n time to detect both static and dynamic pattern-sensitive faults over the 9-neighbourhood of every memory cell. A 4 Mb RAM can be tested by the proposed algorithm several thousand times faster than the conventional sequential algorithms for detecting pattern-sensitive faults. The test speedup has been achieved by writing a test data simultaneously over many cells, and the stored data are tested simultaneously by a parallel comparator and error detector in a read operation. The existing RAM architecture has been modified very little so that the proposed technique can be implemented very easily even in switched-capacitor DRAM (dynamic random-access memory) with low intercell pitch width. The test procedure has also been applied to built-in self-testing (BIST) and is compared with other BIST implementations. >

A storage-node-boosted RAM with word-line delay compensation

A storage-node-boosted (SNB) RAM has been proposed and its advantages have been made clear for the VLSI memory. The new dynamic RAM architecture features the pulsed cell plates rather than the fixed potential cell plates, which stores 1.7 V/SUB DD/ for `H' in the cell without any boosted clocks and compensates the word-line delay. The 1 kbit test array has been fabricated with a 2 /spl mu/m level design rule. It provides a signal charge level of over 300 fC and a speed-up of 20 ns in a reading operation compared with the fixed cell plate potential cell.